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BGY585A GB302 WT78L05G AP4503 2SD1857 MANY254A LV102 JAN2003J
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  october 2010 doc id 11928 rev 7 1/236 1 st7l34, st7l35 st7l38, st7l39 8-bit mcu for automotive with single voltage flash/rom, data eeprom, adc, timers, spi, linsci? features memories ? 8 kbytes program memory: single voltage extended flash (xflash) or rom with readout protection capa bility. in-application programming and in-circuit programming (iap and icp) for xflash devices ? 384 bytes ram ? 256 bytes data eeprom (xflash and rom devices) with readout protection, 300 k write/erase cycles guaranteed ? xflash and eeprom data retention 20 years at 55c clock, reset and supply management ? enhanced reset system ? enhanced low voltage supervisor (lvd) for main supply and an auxiliary voltage detector (avd) with interrupt capability for implementing safe power-down procedures ? clock sources: internal 1% rc oscillator, crystal/ceramic resonato r or external clock ? optional x8 pll for 8 mhz internal clock ? 5 power saving modes: halt, active halt, auto wakeup from halt, wait and slow i/o ports ? up to 15 multifunctional bidirectional i/o lines ?7 high sink outputs 5 timers ? configurable watchdog timer ? two 8-bit lite timers with prescaler, 1 real- time base and 1 input capture ? two 12-bit autoreload timers with 4 pwm outputs, 1 input capture and 4 output compare functions 2 communication interfaces ? master/slave linsci? asynchronous serial interface ? spi synchronous serial interface interrupt management ? 10 interrupt vectors plus trap and reset ? 12 external interrupt lines (on 4 vectors) a/d converter ? 7 input channels ? 10-bit resolution instruction set ? 8-bit data manipulation ? 63 basic instructions with illegal opcode detection ? 17 main addressing modes ? 8 x 8 unsigned multiply instructions development tools ? full hardware/software development package ? dm (debug module) so20 300 mil qfn20 www.st.com
contents st7l34, st7l35, st7l38, st7l39 2/236 doc id 11928 rev 7 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.1 parametric data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2 debug module (dm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.1 in-circuit programming (icp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.2 in-application programming (iap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5 memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5.1 readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5.2 flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.5 access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.6 data eeprom readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
st7l34, st7l35, st7l38, st7l39 contents doc id 11928 rev 7 3/236 6.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 internal rc oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.4.1 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.4.2 crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.4.3 internal rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.5 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.5.2 asynchronous external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.5.3 external power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.5.4 internal low voltage detector (lvd) reset . . . . . . . . . . . . . . . . . . . . . . . . 45 7.5.5 internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.6 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.6.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.6.2 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.6.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.6.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.1 non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.3 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.4 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.4.1 halt mode recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.5 active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.6 auto wakeup from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
contents st7l34, st7l35, st7l38, st7l39 4/236 doc id 11928 rev 7 10 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.2.1 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.2.2 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.4 unused i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.7 device-specific i/o port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.1.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.1.4 hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.1.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.1.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.2 dual 12-bit autoreload timer 3 (at3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.2.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.2.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.2.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.2.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.3 lite timer 2 (lt2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 11.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 11.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 11.3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.3.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.3.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
st7l34, st7l35, st7l38, st7l39 contents doc id 11928 rev 7 5/236 11.4.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.4.4 clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.4.5 error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.4.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.4.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.4.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.5 linsci serial communication interface (l in master/slave) . . . . . . . . . . 123 11.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 11.5.2 sci features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 11.5.3 lin features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 11.5.4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.5.5 sci mode - functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 11.5.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 11.5.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.5.8 sci mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.5.9 lin mode - functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.5.10 lin mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 11.6 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 11.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 11.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 11.6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 11.6.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.6.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 12.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 12.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 12.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 12.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 12.1.4 indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 12.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 12.1.6 indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 12.1.7 relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 12.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 12.2.1 using a prebyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 12.2.2 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
contents st7l34, st7l35, st7l38, st7l39 6/236 doc id 11928 rev 7 13 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.2.1 voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.2.2 current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 13.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 13.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 13.3.2 operating conditions with low voltage detector (lvd) . . . . . . . . . . . . . 188 13.3.3 auxiliary voltage detector (avd) thresholds . . . . . . . . . . . . . . . . . . . . . 190 13.3.4 internal rc oscillator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.4.1 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.4.2 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 13.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 13.5.1 general timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 13.5.2 crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 196 13.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 13.6.1 ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 13.6.2 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 13.6.3 eeprom data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 13.7 electromagnetic compatability (emc) char acteristics . . . . . . . . . . . . . . 198 13.7.1 functional electr omagnetic susceptibility (ems) . . . . . . . . . . . . . . . . . 198 13.7.2 electromagnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.7.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 200 13.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 13.8.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 13.8.2 output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 13.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 13.9.1 asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 13.10 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 209
st7l34, st7l35, st7l38, st7l39 contents doc id 11928 rev 7 7/236 13.10.1 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 13.11 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 14 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 14.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 14.2 packaging for automatic handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 14.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 15 device configuration and ordering informati on . . . . . . . . . . . . . . . . . 217 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 15.2 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 15.2.1 flash option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 15.2.2 rom option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 15.3 device ordering information and transfer of customer code . . . . . . . . . . 221 15.4 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.4.1 starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.4.2 development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.4.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.4.4 order codes for development and programming tools . . . . . . . . . . . . . 227 16 important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 16.1 clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . 228 16.2 linsci limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 16.2.1 header time-out does not prevent wake-up from mute mode . . . . . . . 228 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
list of tables st7l34, st7l35, st7l38, st7l39 8/236 doc id 11928 rev 7 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2. device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3. hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. eecsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5. data eeprom register map and re set values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 6. cc register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 7. rccr calibration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 8. mccsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 9. rccr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 10. clock cycle delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 11. effect of low power modes on system integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 12. supply, reset and clock ma nagement interrup t control/wake-up capability . . . . . . . . . . . . 48 table 13. sicsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 14. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 15. eicr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 16. interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 17. eisr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 18. ltcsr/atcsr register status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 19. awucsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 20. awupr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 21. awupr dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 22. awu register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 table 23. dr value and output pin status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 24. i/o port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 25. i/o configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 26. effect of low power modes on i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 table 27. i/o interrup t control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 28. port configuration (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 29. port configuration (external interrupts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 30. i/o port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 31. watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 32. wdgcr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 33. watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 34. effect of low power modes on at3 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 35. at3 interrupt control/ wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 36. atcsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 37. cntr1h and cntr1l register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 38. atr1h and atr1l register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 39. pwmcr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 40. pwmxcsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 41. breakcr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 42. dcrxh and dcrxl register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 43. aticrh and aticrl register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 44. atcsr2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 45. atr2h and atr2l register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 46. dtgr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 47. register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 48. effect of low power modes on lite timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
st7l34, st7l35, st7l38, st7l39 list of tables doc id 11928 rev 7 9/236 table 49. lite timer 2 interrupt control/wa ke-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 50. ltcsr2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 51. ltarr register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 52. ltcntr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 53. ltcsr1 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 54. lticr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 55. lite timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 table 56. effect of low power modes on spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 18 table 57. spi interrupt control/ wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 table 58. spicr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 59. spicsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 60. spi register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 61. character formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 62. effect of low power modes on sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 34 table 63. sci interrupt c ontrol/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 table 64. scisr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 65. scicr1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 66. scicr2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 67. scibrr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 68. scierpr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 69. scietpr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 70. scisr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 71. scicr1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 72. scicr2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 73. scicr3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 74. lpr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 75. lin mantissa rounded values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 76. lpfr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 77. ldiv fractions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 78. lhlr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 79. lin header mantissa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 80. lin header fractions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 81. linsci1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 82. effect of low power modes on the a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 83. adccsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 84. adcdrh register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 85. adcdrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 86. adc clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 87. adc register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 0 table 88. cpu addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 71 table 89. cpu addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 90. inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 91. immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 92. instructions supporting direct, indexed, in direct and indirect indexed addressing modes 175 table 93. short instructions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 94. relative mode instructions (direct and indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 95. instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 96. instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 97. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 98. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 99. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 100. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
list of tables st7l34, st7l35, st7l38, st7l39 10/236 doc id 11928 rev 7 table 101. operating conditions (tested for t a = -40 to +125 c) @ v dd = 4.5 to 5.5 v . . . . . . . . . . 185 table 102. operating conditions (tested for t a = -40 to +125 c) @ v dd = 4.5 to 5.5 v . . . . . . . . . . 185 table 103. operating conditions (tested for t a = -40 to +125 c) @ v dd = 3.0 to 3.6 v . . . . . . . . . . 186 table 104. operating conditions (tested for t a = -40 to +125 c) @ v dd = 3.0 to 3.6 v . . . . . . . . . . 187 table 105. operating conditions with low voltage detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 106. auxiliary voltage dete ctor (avd) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 107. internal rc oscillator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 108. supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 109. on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 110. general timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 111. oscillator parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 112. typical ceramic resonator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 table 113. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 114. characteristics of dual voltage hdflash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 115. characteristics of eeprom data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 116. electromagnetic test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 117. emi emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 118. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 00 table 119. latch up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 120. i/o general port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 121. output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 122. asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 123. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 124. 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 125. adc accuracy with 4.5 v < v dd < 5.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 126. adc accuracy with 3 v < v dd < 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 127. 20-pin plastic small outline package, 300-mil width, mechanical data . . . . . . . . . . . . . . . 214 table 128. qfn 5x6: 20-terminal very thin fine pitch quad flat no-lead package . . . . . . . . . . . . . . . . 215 table 129. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 130. flash and rom option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 table 131. option byte 0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 table 132. option byte 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 133. option byte 0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 134. option byte 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 table 135. st7l3 development and programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 136. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
st7l34, st7l35, st7l38, st7l39 list of figures doc id 11928 rev 7 11/236 list of figures figure 1. general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 2. 20-pin so package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3. 20-pin qfn package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5. typical icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6. eeprom block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 7. data eeprom programmin g flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 8. data eeprom write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9. data eeprom programmin g cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 10. cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 11. stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 12. pll output frequency timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 13. clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 figure 14. st7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 15. reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 16. reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 17. reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 18. low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 19. reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 20. using the avd to monitor v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 21. interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 22. power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 23. slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 24. wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 25. halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 26. halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 27. active halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 28. active halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 29. awufh mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 30. awuf halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 31. awufh mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 32. i/o port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 33. interrupt i/o port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 34. watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 35. single timer mode (encntr2 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 36. dual timer mode (encntr2 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 37. pwm polarity inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 38. pwm function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 39. pwm signal from 0% to 100%duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 40. dead time generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 41. block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 42. block diagram of output compare mode (single timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 43. block diagram of input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 44. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 45. long range input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 46. long range input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 47. lite timer 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 48. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
list of figures st7l34, st7l35, st7l38, st7l39 12/236 doc id 11928 rev 7 figure 49. serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 0 figure 50. single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 51. generic ss timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 52. hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 53. data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 54. clearing the wcol bit (wri te collision flag) so ftware sequence . . . . . . . . . . . . . . . . . . . . 117 figure 55. single master/multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 56. sci block diagram (in conventional baud rate generator mode). . . . . . . . . . . . . . . . . . . . 126 figure 57. word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 58. sci baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 59. lin characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 60. sci block diagram in lin slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 figure 61. lin header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 62. lin identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 63. lin header reception timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 64. lin synch field measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 65. ldiv read/write operations when ldum = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 66. ldiv read/write operations when ldum = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 67. bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 68. lsf bit set and clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 69. adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 70. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 71. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 72. f clkin maximum operating frequency vs v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . 184 figure 73. typical accuracy with rccr = rccr0 vs v dd = 4.5 to 5.5 v and temperature . . . . . . . 186 figure 74. f rc vs v dd and temperature for calibrated rccr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 figure 75. typical accuracy with rccr = rccr1 vs vdd = 3 to 3.6 v and temperature . . . . . . . . 187 figure 76. f rc vs v dd and temperature for calibrated rccr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 77. pll x 8 output vs clkin frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 88 figure 78. typical i dd in run mode vs f cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 79. typical i dd in slow mode vs f cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 80. typical i dd in wait mode vs f cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 81. typical i dd in slow-wait mode vs f cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 figure 82. typical i dd vs temperature at v dd = 5 v and f clkin = 16 mhz. . . . . . . . . . . . . . . . . . . . . 193 figure 83. typical i dd vs temperature and v dd at f clkin = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . 193 figure 84. two typical applications with unused i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 figure 85. typical i pu vs v dd with v in = v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 86. typical v ol at v dd = 3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 87. typical v ol at v dd = 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 88. typical v ol at v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 89. typical v ol at v dd = 3 v (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 90. typical v ol at v dd = 4 v (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 91. typical v ol at v dd = 5 v (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 92. typical v dd - v oh at v dd = 3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 93. typical v dd - v oh at v dd = 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 94. typical v dd - v oh at v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 95. typical v ol vs v dd (standard i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 96. typical v dd -v oh vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 97. reset pin protection when lvd is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 98. reset pin protection when lvd is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 99. spi slave timing diagram with cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 figure 100. spi slave timing diagram with cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
st7l34, st7l35, st7l38, st7l39 list of figures doc id 11928 rev 7 13/236 figure 101. spi master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 102. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 103. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 104. 20-pin plastic small outline package, 300-mil width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 figure 105. qfn 5x6, 20-terminal very thin fine pitch quad flat no-lead package . . . . . . . . . . . . . . . . 215 figure 106. pin 1 orientation in tape and reel conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 figure 107. st7fl3x flash commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 figure 108. st7fl3x fastrom commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 figure 109. rom commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 figure 110. header reception event sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 figure 111. linsci interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
description st7l34, st7l35, st7l38, st7l39 14/236 doc id 11928 rev 7 1 description the st7l3x is a member of the st7 microcontroller family suitable for automotive applications. all st7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. the st7l3x features flash memory with byte-by-byte in-circuit programming (icp) and in- application programm ing (iap) capability. under software control, the st7l3x devices can be placed in wait, slow or halt mode, reducing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling th e design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. 1.1 parametric data for easy reference, all para metric data is located in section 13: electrical characteristics . 1.2 debug module (dm) the devices feature an on-chip debug module (dm) to support in-circuit debugging (icd). for a description of the dm registers, refer to the st7 icc protocol reference manual . table 1. device summary feature st7l34 st7l35 st7l38 st7l39 program memory 8 kbytes ram (stack) 384 bytes (128 bytes) data eeprom - 256 bytes peripherals lite timer, autoreload timer, spi, 10-bit adc lite timer, autoreload timer, spi, 10-bit adc, linsci lite timer, autoreload timer, spi, 10-bit adc lite timer, autoreload timer, spi, 10-bit adc, linsci operating supply 3.0 v to 5.5 v cpu frequency up to 8 mhz (with external re sonator/clock or internal rc oscillator) operating temperature up to -40 to 85c / -40 to 125c packages so20 300mil, qfn20
st7l34, st7l35, st7l38, st7l39 description doc id 11928 rev 7 15/236 figure 1. general block diagram 8-bit core alu address and data bus osc1 osc2 reset port a internal clock control ram (384 bytes) pa7:0 (8 bits) v ss v dd power supply program (8 kbytes) lvd memory pll x8 ext. 1mhz int. 1mhz 8-bit lite timer 2 port b spi pb6:0 (7 bits) 1% rc osc to 16 mhz adc 12-bit autoreload timer 3 clkin /2 watchdog debug module data eeprom (128 bytes) linsci
pin description st7l34, st7l35, st7l38, st7l39 16/236 doc id 11928 rev 7 2 pin description figure 2. 20-pin so package pinout 1. eix: associated external interrupt vector 2. (hs): 20ma high sink capability figure 3. 20-pin qfn package pinout 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 v ss v dd ain5/pb5 clkin/ain4/pb4 mosi/ain3/pb3 miso/ain2/pb2 sck/ain1/pb1 ss /ain0/pb0 osc1/clkin osc2 pa 5 (hs)/atpwm3/iccdata pa 4 (hs)/atpwm2 pa 3 (hs)/atpwm1 pa 2 (hs)/atpwm0 pa 1 (hs)/atic pa 0 (hs)/ltic ) 12 11 9 10 rdi/ain6/pb6 pa 7 ( h s ) / t d o pa6/mco/iccclk/break reset ei3 ei2 ei0 ei1 ei2 (hs) 20ma high sink capability eix associated external interrupt vector v dd 6 7 8 9 ei2 10 11 clkin/ain4/pb4 ei1 12 pa1 (hs)/atic pa2 (hs)/atpwm0 pa3 (hs)/atpwm1 pa4 (hs)/atpwm2 pa5 (hs)/atpwm3/iccdata 13 14 15 ei0 16 pa0 (hs)/ltic 20 18 17 19 v ss osc1/clkin osc2 1 2 ei3 reset ss/ain0/pb0 3 4 5 ei2 sck/ain1/pb1 miso/ain2/pb2 mosi/ain3/pb3 ain5/pb5 rdi/ain6/pb6 pa7(hs)/tdo pa6/mco/iccclk/break
st7l34, st7l35, st7l38, st7l39 pin description doc id 11928 rev 7 17/236 legend/abbreviations for ta b l e 2 : type: i = input, o = output, s = supply input/output level: c t =cmos 0.3 v dd /0.7 v dd with input trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration inputs: float = floating, wpu = weak pull-up, int = interrupt, ana = analog ports port and control configuration outputs: od = open drain, pp = push-pull note: the reset configuration of each pin (shown in bold) is valid as long as the device is in reset state. table 2. device pin description pin no. pin name type level port/control main function (after reset) alternate function so20 qfn20 input output input (1) output float wpu int ana od pp 119v ss s ground 220v dd s main power supply 3 1 reset i/o c t xx top priority non maskable interrupt (active low) 4 2 pb0/ain0/ss i/o c t x ei3 xxxport b0 adc analog input 0 or spi slave select (active low) 5 3 pb1/ain1/sck i/o c t xxxxport b1 adc analog input 1 or spi serial clock 6 4 pb2/ain2/miso i/o c t xxxxport b2 adc analog input 2 or spi master in/slave out data 7 5 pb3/ain3/mosi i/o c t xei2xxxport b3 adc analog input 3 or spi master out/slave in data 8 6 pb4/ain4/clkin/ i/o c t xx xxxport b4 adc analog input 4 or external clock input 9 7 pb5/ain5 i/o c t x ei2 x x x port b5 adc analog input 5 10 8 pb6/ain6/rdi i/o c t xxxxport b6 adc analog input 6 or linsci input 11 9 pa7/tdo i/o c t hs x x x x port a7 linsci output
pin description st7l34, st7l35, st7l38, st7l39 18/236 doc id 11928 rev 7 12 10 pa6 /mco/iccclk/ break i/o c t x ei1 xxport a6 main clock output or in- circuit communication clock or external break caution: during normal operation this pin must be pulled- up, internally or externally (external pull-up of 10 k mandatory in noisy environment). this is to avoid entering icc mode unexpectedly during a reset. in the application, even if the pin is configured as output, any reset puts it back in input pull-up 13 11 pa5/iccdata/ at p w m 3 i/o c t hs x x x port a5 autoreload timer pwm3 or in-circuit communication data 14 12 pa4/atpwm2 i/o c t hs x x x port a4 autoreload timer pwm2 15 13 pa3/atpwm1 i/o c t hs x ei0 x x port a3 autoreload timer pwm1 16 14 pa2/atpwm0 i/o c t hs x x x port a2 autoreload timer pwm0 17 15 pa1/atic i/o c t hs x x x port a1 autoreload timer input capture 18 16 pa0/ltic i/o c t hs x x x x port a0 lite timer input capture 19 17 osc2 o resonator oscillator inverter output 20 18 osc1/clkin i x resonator oscillator inverter input or external clock input 1. for input with inte rrupt possibility ?ei x ? defines the associated external interrupt vector which can be assigned to one of the i/o pins using the eisr regist er. each interrupt can be eit her weak pull-up or floating defined through option register or. table 2. device pin description (continued) pin no. pin name type level port/control main function (after reset) alternate function so20 qfn20 input output input (1) output float wpu int ana od pp
st7l34, st7l35, st7l38, st7l39 register and memory map doc id 11928 rev 7 19/236 3 register and memory map as shown in figure 4 , the mcu can address 64 kbytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, 384 bytes of ram, 256 bytes of data eeprom and up to 8 kbytes of us er program memory. the ram space includes up to 128 bytes for the stack from 180h to 1ffh. the highest address bytes contain the user reset and interrupt vectors. the flash memory contains two sectors (see figure 4 ) mapped in the upper part of the st7 addressing space so the reset and interrupt vectors are located in sector 0 (f000h-ffffh). the size of flash sector 0 and other device options are configurable by option byte (refer to section 15.2: option bytes on page 217 ). note: memory locations marked as ?reserved? must never be access ed. accessing a reserved area can have unpredictable effects on the device. figure 4. memory map 1. dee0h, dee1h, dee2h and dee3h addresses are located in a reserved area but are special bytes containing also the rc calibration values which are read-accessi ble only in user mode. if all the eeprom data or flash space (including the rc calibration values locations) has been erased (after the readout protection remova l), then the rc calibrat ion values can still be obtained through these four addresses. 0000h ram flash memory (8k) interrupt and reset vectors hw registers 0080h 007fh 0fffh (see ta bl e 3 ) 1000h 10ffh ffe0h ffffh (see ta b l e 1 4 ) 0200h reserved 01ffh short addressing ram (zero page) 128 bytes stack 0180h 01ffh 0080h 00ffh (384 bytes) e000h 1100h dfffh reserved ffdfh 16-bit addressing ram 0100h 017fh 1 kbyte 7 kbytes sector 1 sector 0 8k flash ffffh fc00h fbffh e000h program memory data eeprom (256 bytes) dee0h rccrh1 rccrl1 see note 1 below and section 7.1 on page 38 dee1h dee2h rccrh0 rccrl0 dee3h dee4h
register and memory map st7l34, st7l35, st7l38, st7l39 20/236 doc id 11928 rev 7 legend for ta bl e 3 : x = undefined, r/w = read/write, ro = read only table 3. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a pa d r paddr pao r port a data register port a data direction register port a option register ffh (1) 00h 40h r/w r/w r/w 0003h 0004h 0005h port b pbdr pbddr pbor port b data register port b data direction register port b option register ffh (1) 00h 00h r/w r/w r/w (2) 0006h 0007h reserved area (2 bytes) 0008h 0009h 000ah 000bh 000ch lite timer 2 ltcsr2 lta r r lt c n t r ltcsr1 lt i c r lite timer control/status register 2 lite timer autoreload register lite timer counter 2 register lite timer control/status register 1 lite timer input capture register 0fh 00h 00h 0x00 0000b xxh r/w r/w ro r/w ro 000dh 000eh 000fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh 0020h 0021h 0022h 0023h 0024h 0025h auto- reload timer 3 at c s r cntr1h cntr1l at r 1 h at r 1 l pwmcr pwm0csr pwm1csr pwm2csr pwm3csr dcr0h dcr0l dcr1h dcr1l dcr2h dcr2l dcr3h dcr3l aticrh aticrl atcsr2 breakcr at r 2 h at r 2 l dtgr timer control/status register counter register 1 high counter register 1 low autoreload register 1 high autoreload register 1 low pwm output control register pwm 0 control/status register pwm 1 control/status register pwm 2 control/status register pwm 3 control/status register pwm 0 duty cycle register high pwm 0 duty cycle register low pwm 1 duty cycle register high pwm 1 duty cycle register low pwm 2 duty cycle register high pwm 2 duty cycle register low pwm 3 duty cycle register high pwm 3 duty cycle register low input capture register high input capture register low timer control/status register 2 break control register autoreload register 2 high autoreload register 2 low dead time generator register 0x00 0000b 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 03h 00h 00h 00h 00h r/w ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro r/w r/w r/w r/w r/w 0026h to 002dh reserved area (8 bytes) 002eh wdg wdgcr watchdog control register 7fh r/w 0002fh flash fcsr flash control/status register 00h r/w 00030h eeprom eecsr data eeprom control/status register 00h r/w
st7l34, st7l35, st7l38, st7l39 register and memory map doc id 11928 rev 7 21/236 0031h 0032h 0033h spi spidr spicr spicsr spi data i/o register spi control register spi control/status register xxh 0xh 00h r/w r/w r/w 0034h 0035h 0036h adc adccsr adcdrh adcdrl a/d control/status register a/d data register high a/d control and data register low 00h xxh x0h r/w ro r/w 0037h itc eicr external interrupt control register 00h r/w 0038h mcc mccsr main clock control/status register 00h r/w 0039h 003ah clock and reset rccr sicsr rc oscillator control register system integrity control/status register ffh 0110 0xx0b r/w r/w 003bh reserved area (1 byte) 003ch itc eisr external interrupt selection register 00h r/w 003dh to 003fh reserved area (3 bytes) 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h linsci (lin master/ slave) scisr scidr scibrr scicr1 scicr2 scicr3 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci control register 3 sci extended receive prescaler register sci extended transmit prescaler register c0h xxh 00xx xxxxb xxh 00h 00h 00h 00h ro r/w r/w r/w r/w r/w r/w r/w 0048h reserved area (1 byte) 0049h 004ah awu awupr awucsr awu prescaler register awu control/status register ffh 00h r/w r/w 004bh 004ch 004dh 004eh 004fh 0050h dm (3) dmcr dmsr dmbk1h dmbk1l dmbk2h dmbk2l dm control register dm status register dm breakpoint register 1 high dm breakpoint register 1 low dm breakpoint register 2 high dm breakpoint register 2 low 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w 0051h to 007fh reserved area (47 bytes) 1. the contents of the i/o port dr registers are readable onl y in output configuration. in input configuration, the values of the i/o pins are retur ned instead of the dr register contents 2. the bits associated with unavailable pins must alwa ys keep their reset value 3. for a description of the debug module registers, see st7 icc protocol reference manual table 3. hardware register map (continued) address block register label register name reset status remarks
flash program memory st7l34 , st7l35, st7l38, st7l39 22/236 doc id 11928 rev 7 4 flash program memory 4.1 introduction the st7 single voltage extended flash (xflash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. the xflash devices can be programmed off-board (plugged in a programming tool) or on- board using in-circuit programming (icp) or in-application programming (iap). the array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features in-circuit programming (icp) in-application programming (iap) in-circuit testing (ict) for downloading and executing user application test patterns in ram sector 0 size configurable by option byte readout and write protection 4.3 programming modes the st7 can be programmed in three different ways: ? insertion in a programming tool. in this mode, flash sectors 0 and 1, option byte row and data eeprom (if present) can be programmed or erased. ? in-circuit programming. in this mode, flash sectors 0 and 1, option byte row and data eeprom (if present) ca n be programmed or eras ed without removing the device from the application board. ? in-application programming. in this mode, sector 1 and data eeprom (if present) can be programmed or erased without removing the device from the application board and while the application is running. 4.3.1 in-circuit programming (icp) icp uses a protocol called icc (in-circuit communication) which allows an st7 plugged on a printed circuit board (pcb) to communicate with an external programming device connected via a cable. icp is performed in three steps: ? switch the st7 to icc mode (in-circuit co mmunications). this is done by driving a specific signal sequ ence on the iccclk/data pins while the reset pin is pulled low. when the st7 enters icc mode, it fetches a specific reset vector which points to the st7 system memory containing the icc protocol routine. this routine enables the st7 to receive bytes from the icc interface. ? download icp driver code in ram from the iccdata pin ? execute icp driver code in ram to program the flash memory
st7l34, st7l35, st7l38, st7l39 flash program memory doc id 11928 rev 7 23/236 depending on the icpdriver code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 in-application programming (iap) this mode uses an iap driver program previously programmed in sector 0 by the user (in icp mode). iap mode is fully controlled by user software, allowing it to be adapted to the user application (such as a user-defined strategy for entering programming mode or a choice of communications protocol used to fetch the data to be stored). this mode can be used to program any memory areas except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.4 icc interface icp needs a minimum of four and up to six pins to be connected to the programming tool. these pins are: ? reset : device reset ?v ss : device power supply ground ? iccclk: icc output serial clock pin ? iccdata: icc input serial data pin ? clkin/pb4: main clock input for external source ?v dd : application board power supply (optional, see note 3, figure 5: typical icc interface on page 24 )
flash program memory st7l34 , st7l35, st7l38, st7l39 24/236 doc id 11928 rev 7 figure 5. typical icc interface 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programming tool is plugged to the board, even if an icc sess ion is not in progress, the iccclk and iccdata pins are not available for the application. if they ar e used as inputs by the appl ication, isolation such as a serial resistor must be implemented in case another device forces the signal. re fer to the programming tool documentation for recommended resistor values. 2. during the icp session, the programming tool must control the reset pin. this can lead to conflicts between the programming tool and the application reset ci rcuit if it drives more than 5 ma at high level (push-pull output or pull-up resistor < 1k). a schottky diode can be used to isolate the application reset circuit in this case. when using a classical rc network with r > 1k or a reset management ic with open dr ain output and pull-up resistor > 1k, no additional components are needed. in all cases the user must ensure that no exter nal reset is generated by the appl ication during the icc session. 3. the use of pin 7 of the icc connector depends on the programmi ng tool architecture. this pin must be connected when using most st programming tools (it is used to monitor the application power suppl y). please refer to the programming tool manual. 4. pin 9 must be connected to the pb4 pin of the st7 when the cloc k is not available in the application or if the selected clock option is not programmed in the option by te. st7 devices with mult i-oscillator capability must have osc2 grounded in this case. 5. with any programming tool, while the icp option is di sabled, the external cloc k must be provided on pb4. 6. in icc mode, the internal rc oscillator is forced as a cl ock source, regardless of the selection in the option byte. caution: during normal operation the iccclk pin must be pulled up, internally or externally (external pull-up of 10k mandatory in noisy environment). this is to avoid entering icc mode unexpectedly during a reset. in the application, even if the pin is configured as output, any reset puts it back in input pull-up. icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) st7 clkin/pb4 optional see note 1 see note 1 and caution see note 2 application reset source application i/o (see note 4) (see note 5)
st7l34, st7l35, st7l38, st7l39 flash program memory doc id 11928 rev 7 25/236 4.5 memory protection there are two different types of memory protection: readout protection and write/erase protection, which can be applied individually. 4.5.1 readout protection readout protection, when selected, protects against program memory content extraction and against write access to flash memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. both program and data ee memory are protected. in flash devices, this protection is removed by reprogramming the option. in this case, both program and data ee memory are automatically erased and the device can be reprogrammed. readout protection selection depends on the device type: in flash devices it is enabled and removed through the fmp_r bit in the option byte. in rom devices it is enabled by the mask option specified in the option list. 4.5.2 flash write/erase protection write/erase protection, when set, makes it impossible to both overwrite and erase program memory. it does not apply to ee data. its purpose is to provide advanced security to applications and prevent any change being made to the memory content. warning: once set, write/erase protection can never be removed. a write-protected flash device is no longer reprogrammable. write/erase protection is enabled through the fmp_w bit in the option byte. 4.6 related documentation for details on flash programming and icc protocol, refer to the st7 flash programming reference manual and to the st7 icc protocol reference manual .
flash program memory st7l34 , st7l35, st7l38, st7l39 26/236 doc id 11928 rev 7 4.7 register description flash control/status register (fcsr) note: this register is reserved for programming using icp, iap or other programming methods. it controls the xflash programming and erasing operations. when an epb or another programm ing tool is used (in socket or icp mode), the rass keys are sent automatically. fcsr reset value: 0000 0000 (00h) 1st rass key: 0101 0110 (56h) 2nd rass key: 10101110 (aeh) 76543210 reserved reserved reserved reserved reserved opt lat pgm -----r/wr/wr/w
st7l34, st7l35, st7l38, st7l39 data eeprom doc id 11928 rev 7 27/236 5 data eeprom 5.1 introduction the electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. using the eeprom requires a basic access protocol described in this chapter. 5.2 main features up to 32 bytes programmed in the same cycle eeprom mono-voltage (charge pump) chained erase and programming cycles internal control of the global programming cycle duration wait mode management readout protection figure 6. eeprom block diagram eecsr high voltage pump 0 e2lat 0 0 0 0 0 e2pgm eeprom memory matrix (1 row = 32 x 8 bits) address decoder data multiplexer 32 x 8 bits data latches row decoder data bus 4 4 4 128 128 address bus
data eeprom st7l34, st 7l35, st7l38, st7l39 28/236 doc id 11928 rev 7 5.3 memory access the data eeprom memory read/write access modes are controlled by the e2lat bit of the eeprom control/status register (eecsr). the flowchart in figure 7: data eeprom programming flowchart on page 29 describes these different memory access modes. read operation (e2lat = 0) the eeprom can be read as a normal rom lo cation when the e2lat bit of the eecsr register is cleared. on this device, data eeprom ca n also be used to execute ma chine code. do not write to the data eeprom while ex ecuting from it. this would resu lt in an unexpected code being executed. write operation (e2lat = 1) to access the write mode, the e2lat bit must be set by software (the e2pgm bit remains cleared). when a write access to the eeprom ar ea occurs, the value is latched inside the 32 data latches according to its address. when pgm bit is set by the software, all the prev ious bytes written in the data latches (up to 32) are programmed in the eeprom cells. the effective high address (row) is determined by the last eeprom write sequence. to avoid wrong programming, th e user must ensure that all the bytes written between two programming sequences have the same high address: only the five least si gnificant bits of the address can change. at the end of the programming cycle, the pgm and lat bits are cleared simultaneously. note: care should be taken during the programming cycle. writing to the same memory location over-programs the memory (logical and between the two write access data results) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the e2lat bit. it is not possi ble to read the latched data. this note is illustrated by figure 9: data eeprom programming cycle on page 31 .
st7l34, st7l35, st7l38, st7l39 data eeprom doc id 11928 rev 7 29/236 figure 7. data eeprom programming flowchart figure 8. data eeprom write operation 1. if a programming cycle is interrupted (b y a reset action), the integrity of the data in memory is not guaranteed. read mode e2lat = 0 e2pgm = 0 write mode e2lat = 1 e2pgm = 0 read bytes in eeprom area writeupto32bytes in eeprom area (with the same 11 msb of the address) start programming cycle e2lat = 1 e2pgm = 1 (set by software) e2lat 01 cleared by hardware byte 1 byte 2 byte 32 phase 1 programming cycle read operation impossible phase 2 read operation possible e2lat bit e2pgm bit writing data latches waiting e2pgm and e2lat to fall set by user application cleared by hardware ? row/byte ? 0 1 2 3 ... 30 31 physical address 0 00h...1fh 1 20h...3fh ... n nx20h...nx20h+1fh row definition
data eeprom st7l34, st 7l35, st7l38, st7l39 30/236 doc id 11928 rev 7 5.4 power saving modes wait mode the data eeprom can ent er wait mode on execution of the wfi instruction of the microcontroller or wh en the microcontroller enters acti ve halt mode.the data eeprom immediately enters this mode if there is no programming in progress, otherwise the data eeprom finishes the cycle and then enters wait mode. active halt mode refer to wait mode. halt mode the data eeprom immediately ent ers halt mode if the microc ontroller executes the halt instruction. therefore, the eeprom stops the function inprogress , and data may be corrupted. 5.5 access error handling if a read access occurs while e2lat = 1, then the data bus is not driven. if a write access occurs while e2lat = 0, then the data on the bus is not latched. if a programming cycle is interrupted (by reset action), the integrity of the data in memory is not guaranteed. 5.6 data eeprom readout protection the readout protection is enabled through an option bit (see section 15.2: option bytes on page 217 ). when this option is selected, the programs and data stored in the eeprom memory are protected against readout (including a rewrit e protection). in flash devices, when this protection is removed by reprogramming the option byte, the entire program memory and eeprom is first automatically erased. note: both program memory and data eeprom are protected using the same option bit.
st7l34, st7l35, st7l38, st7l39 data eeprom doc id 11928 rev 7 31/236 figure 9. data eeprom programming cycle 5.7 register description eeprom control/status register (eecsr) eecsr reset value: 0000 0000 (00h) 76543210 reserved reserved reserved reserved reserved reserved e2lat e2pgm ------r/wr/w table 4. eecsr register description bit bit name function 7:2 - reserved, forced by hardware to 0 1 e2lat latch access transfer this bit is set by software. it is cleared by hardware at the end of the programming cycle. it can only be cleared by software if the e2pgm bit is cleared. 0: read mode 1: write mode 0e2pgm programming control and status this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is cleared by hardware. 0: programming finished or not yet started 1: programming cycle is in progress note: if the e2pgm bit is cleared during the programming cycle, the memory data is not guaranteed lat erase cycle write cycle pgm t prog read operation not possible write of data latches read operation possible internal programming voltage
data eeprom st7l34, st 7l35, st7l38, st7l39 32/236 doc id 11928 rev 7 table 5. data eeprom register map and reset values address (hex.)register label765432 1 0 0030h eecsr reset value 000000 e2lat 0 e2pgm 0
st7l34, st7l35, st7l38, st7l39 central processing unit doc id 11928 rev 7 33/236 6 central processing unit 6.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 6.2 main features 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes two 8-bit index registers 16-bit stack pointer low power modes maskable hardware interrupts non-maskable software interrupt 6.3 cpu registers the six cpu registers shown in figure 10 are not present in the memory mapping and are accessed by specific instructions. figure 10. cpu registers 1. x = undefined value accumulator register x index register y index register stack pointer register condition code register program counter regsiter 70 1c 11hinz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh
central processing unit st7l34, st7l35, st7l38, st7l39 34/236 doc id 11928 rev 7 accumulator register (a) the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the following instruction refers to the y register.) the y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). program counter register (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers, pcl (program counter low which is the lsb) and pch (program counter high which is the msb). condition code register (cc) the 8-bit condition code register contains the interrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop instructions. these bits can be individually tested and/or controlled by specific instructions. cc reset value: 111x 1xxx 76543210 111hinzc r/w r/w r/w r/w r/w table 6. cc register description bit bit name function 4h half carry this bit is set by hardware when a carry occurs between bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred 1: a half carry has occurred this bit is tested using the jrh or jrnh instruction. the h bit is useful in bcd arithmetic subroutines.
st7l34, st7l35, st7l38, st7l39 central processing unit doc id 11928 rev 7 35/236 3 i interrupt mask this bit is set by hardware when en tering in interrupt or by software to disable all interrupts except th e trap software interrupt. this bit is cleared by software. 0: interrupts are enabled 1: interrupts are disabled this bit is controlled by the rim, sim and iret instructions and is tested by the jrm and jrnm instructions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptible because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current inte rrupt routine. 2n negative this bit is set and cleared by hardware. it is representative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null 1: the result of the last operation is negative (in other words, the most significant bit is a logic 1) this bit is accessed by the jrmi and jrpl test instructions. 1z zero this bit is set and cleared by hardware. this bit indicates that the result of the last arithmetic, logi cal or data manipulation is zero. 0: the result of the last ope ration is different from zero 1: the result of the last operation is zero this bit is accessed by the jreq and jrne test instructions. 0c carry/borrow this bit is set and cleared by hardware and software. it indicates an overflow or an underflow has occu rred during the last arithmetic operation. 0: no overflow or underflow has occurred 1: an overflow or underflow has occurred this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is al so affected by the ?bit test and branch?, shift and rotate instructions. table 6. cc register description (continued) bit bit name function
central processing unit st7l34, st7l35, st7l38, st7l39 36/236 doc id 11928 rev 7 stack pointer register (sp) the stack pointer is a 16-bit register whichalways points to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 11: stack manipulation example on page 37 ). since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruction (rsp), the stack pointer contains its reset value (the sp6 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld instruction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. the previously stored information is then overwritten and therefore lost. the stack also wraps in case of an underflow. the stack is used to save the return address during a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instructions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 11: stack manipulation example on page 37 . when an interrupt is received, the sp is decremented and the context is pushed on the stack on return from interrupt, the sp is incremented and the context is popped from the stack a subroutine call occupies two locations and an interrupt five locations in the stack area. sp reset value: 01 ffh 15 14 13 12 11 10 9 8 reserved reserved reserved reserved reserved reserved reserved 1 -------r/w 76543210 1 sp[6:0] r/w r/w
st7l34, st7l35, st7l38, st7l39 central processing unit doc id 11928 rev 7 37/236 figure 11. stack manipulation example 1. legend: stack higher address = 01ffh; stack lower address = 0180h pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0180h
supply, reset and clock management st7l34, st7l35, st7l38, st7l39 38/236 doc id 11928 rev 7 7 supply, reset and clock management the device includes a range of utility featur es for securing the application in critical situations (for example, in case of a power brown-out) and reducing the number of external components. main features clock management ? 1 mhz internal rc oscillator (enabled by option byte) ? 1 to 16 mhz or 32 khz external crystal/ceramic resonator (selected by option byte) ? external clock input (enabled by option byte) ? pll for multiplying the frequency by 8(enabled by option byte) reset sequence manager (rsm) system integrity management (si) ? main supply low voltage detection (lvd)with reset generation (enabled by option byte) ? auxiliary voltage detector (avd) with interr upt capability for mo nitoring the main supply (enabled by option byte) 7.1 internal rc oscillator adjustment the device contains an internal rc oscillato r with high accuracy for a given device, temperature and voltage. it must be calibrated to obtain the frequency required in the application. this is done by the software writ ing an 8-bit calibration value in the rccr (rc control register) and in the bits [6:5] in the sicsr (si control status register). whenever the microcontroller is reset, the rccr return s to its default value (ffh), that is, each time the device is reset, the calibration value must be loaded in the rccr. predefined calibration values are stored in eeprom for 3.3 v and 5 v v dd supply voltages at 25c, as shown in ta b l e 7 . table 7. rccr calibration registers rccr conditions st7l3 addresses rccrh0 v dd = 5 v t a = 25c f rc = 1 mhz (1) 1. rccr0 and rccr1 calibrated within these conditions in order to reach rc accuracy as mentioned in table 101: operating conditions (tested for ta = -40 to +125 c) @ vdd = 4.5 to 5.5 v on page 185 and table 103: operating conditions (tested for ta = -40 to +125 c) @ vdd = 3.0 to 3.6 v on page 186 dee0h (2) (cr[9:2] bits) 2. dee0h, dee1h, dee2h and dee3h addresses are lo cated in a reserved area but are special bytes containing also the rc calibration values which are read-accessible only in user mode. if all the eeprom data or flash space (including t he rc calibration values locations) has been erased (after the readout protection removal), then the rc calibration values can still be obtained through these four addresses. for compatibility reasons with the sicsr register, cr[1:0 ] bits are stored in the fi fth and sixth positions of dee1 and dee3 addresses. rccrl0 dee1h (2) (cr[1:0] bits) rccrh1 v dd = 3.3 v t a = 25c f rc = 1 mhz (1) dee2h (2) (cr[9:2] bits) rccrl1 dee3h (2) (cr[1:0] bits)
st7l34, st7l35, st7l38, st7l39 supply, reset and clock management doc id 11928 rev 7 39/236 note: 1 in icc mode, the internal rc oscillator is forced as a clock source, regardless of the selection in the option byte. 2 for more information on the frequency and accura cy of the rc oscillator see section 13: electrical characteristics . 3 to improve clock stability and frequency accura cy, it is recommended to place a decoupling capacitor, typically 100 nf, between the v dd and v ss pins as close as possible to the st7 device. 4 these bytes are systematically programmed by st, including on fastrom devices . consequently, customers intending to use fastrom service must not use these bytes . 5 rccr0 and rccr1 calibration values are not erased if the readout protection bit is reset after it has been set (see section 4.5.1: readout protection on page 25 ). caution: if the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. refer to application note an1324 for information on how to calibrate the rc frequency using an external reference signal. 7.2 phase locked loop the pll can be used to multiply a 1 mhz frequ ency from the rc oscilla tor or the external clock by 8 to obtain an f osc of 8 mhz. the pll is enabled (by 1 option bit) and the multiplication factor is 8. the x8 pll is intended for operation with v dd in the 3.6 v to 5.5 v range . if the pll is disabled and the rc oscillator is enabled, then f osc =1mhz. if both the rc oscillator and the pll are disabled, f osc is driven by the external clock. figure 12. pll output frequency timing diagram when the pll is started, after reset or wakeup from halt mode or awufh mode, it outputs the clock after a delay of t startup . 4/8 x input freq. locked bit set t stab t lock output frequency t startup t
supply, reset and clock management st7l34, st7l35, st7l38, st7l39 40/236 doc id 11928 rev 7 when the pll output signal reaches the operating frequency, the locked bit in the sicscr register is set. full pll accuracy (acc pll ) is reached after a st abilization time of t stab (see figure 12 and section 13.3.4: internal rc oscillator and pll on page 190 ). refer to section 7.6.4: register description on page 49 for a description of the locked bit in the sicsr register. 7.3 register description main clock control/status register (mccsr) rc control register (rccr) mccsr reset value: 0000 0000 (00h) 76543210 reserved reserved reserved reserved reserved reserved mco sms ------r/wr/w table 8. mccsr register description bit bit name function 7:2 - reserved, must be kept cleared 1 mco main clock out enable this bit is read/writen by software and cleared by hardware after a reset. this bit enables the mco output clock. 0: mco clock disabled, i/o port free for general purpose i/o 1: mco clock enabled 0sms slow mode select this bit is read/writen by software and cleared by hardware after a reset. this bit sele cts the input clock f osc or f osc /32. 0: normal mode (f cpu = f osc ) 1: slow mode (f cpu = f osc /32) rccr reset value: 1111 1111 (ffh) 76543210 cr[9:2] r/w
st7l34, st7l35, st7l38, st7l39 supply, reset and clock management doc id 11928 rev 7 41/236 figure 13. clock management block diagram table 9. rccr register description bit bit name function 7:0 cr[9:2] rc oscillator frequency adjustment bits these bits must be written immediately after reset to adjust the rc oscillator frequency and to obtain an accuracy of 1%. the application can store the correct value for each voltage range in eeprom and write it to this register at startup. 00h = maximum available frequency ffh = lowest available frequency these bits are used with the cr[1:0] bits in the sicsr register. refer to section 7.6.4: register description on page 49 . note: to tune the oscillator, write a series of different values in the register until the correct frequency is reached. the fastest method is to use a dichotomy starting with 80h. mccsr sms mco mco f cpu peripherals (1ms timebase @ 8 mhz fosc) /32 divider f osc f osc /32 f osc f lti m e r 8-bit lite timer 2 counter f cpu to cpu and 1 0 cr6 cr9 cr2 cr3 cr4 cr5 cr8 cr7 rccr f osc osc1 osc2 osc 1-16 mhz clkin or 32 khz /2 divider tu n a bl e 1 mhz oscillator 1% rc osc option bit pll 1 mhz -> 8 mhz option bits osc,plloff, oscrange[2:0] /2 divider /32 divider clkin/2 (ext clock) crystal osc /2 rc osc pll clock 8 mhz cr1 cr0 sicsr option bits oscrange[2:0] clkin clkin clkin/ fclkin
supply, reset and clock management st7l34, st7l35, st7l38, st7l39 42/236 doc id 11928 rev 7 7.4 multi-oscillator (mo) the main clock of the st7 can be generated by four different source types coming from the multi-oscillator block (1 to 16 mhz or 32 khz): an external source 5 crystal or ceramic resonator oscillators an internal high frequency rc oscillator each oscillator is optimized fo r a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configurations are shown in table 14: st7 clock sources on page 43 . refer to section 13: electrical characteristics for more details. 7.4.1 external clock source in external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle must drive the osc1 pin while the osc2 pin is tied to ground. note: when the multi-oscillator is not used, pb4 is selected by default as the external clock. 7.4.2 crystal/cer amic oscillators this family of oscillators has the advantage of prod ucing a very accurate rate on the main clock of the st7. the selection within a list of four oscillators with diff erent frequency ranges has to be done by option byte in order to reduce consumption (refer to section 15.2 on page 217 for more details on the frequency ranges). in this mode of the multi-oscillator, the resonator and the load capacitors must be placed as close as possible to the oscillator pins to minimize output distortion and startup stab ilization time. the loadin g capacitance values must be adjusted according to the selected oscillator. these oscillators are not stopped during the rese t phase to avoid losing time in the oscillator startup phase. 7.4.3 internal rc oscillator in this mode, the tunable 1%rc oscillator is the main clock source. the two oscillator pins must be tied to ground. the calibration is done th rough the rccr[7:0] and sicsr[6:5] registers.
st7l34, st7l35, st7l38, st7l39 supply, reset and clock management doc id 11928 rev 7 43/236 7.5 reset sequence manager (rsm) 7.5.1 introduction the reset sequence manager includes three reset sources as shown in figure 16: reset block diagram on page 45 : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset note: a reset can also be triggered following the detection of an illegal op code or prebyte code. refer to section 12.2.2: illegal opcode reset on page 177 for further details. these sources act on the reset pin which is always kept low during the delay phase. the reset service routine vector is fixed at addresses fffeh-ffffh in the st7 memory map. figure 14. st7 clock sources hardware configuration external clock crystal/ceramic resonators internal rc oscillator osc1 osc2 external source st7 osc1 osc2 load capacitors st7 c l2 c l1 osc1 osc2 st7
supply, reset and clock management st7l34, st7l35, st7l38, st7l39 44/236 doc id 11928 rev 7 the basic reset sequence consists of three phases as shown in figure 15 : activephase depending on the reset source 256 or 4096 cpu clock cycle delay (see ta bl e 1 0 ) reset vector fetch caution: when the st7 is unprogrammed or fully erased, the flash is blank and the reset vector is not programmed. for this reason, it is recommended to keep the reset pin in low state until programming mode is entered, in order to avoid unwanted behavior. the 256 or 4096 cpu clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the reset state. the shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte: the reset vector fetch phase duration is two clock cycles. if the pll is enabled by option byte, it outputs the clock after an additional delay of t startup (see figure 12: pll output frequency timing diagram on page 39 ). figure 15. reset sequence phases 7.5.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in accordance with the input voltage. it can be pulled low by external circuitry to reset the device. see section 13: electrical characteristics for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 17: reset sequences on page 46 ). this detection is asynchronous and therefore the mcu can enter the reset state even in halt mode. table 10. clock cycle delays clock source cpu clock cycle delay internal rc oscillator 256 external clock (connected to clkin pin) external crystal/ceramic oscillator (connected to osc1/osc2 pins) 4096 reset active phase internal reset 256 or 4096 clock cycles fetch vector
st7l34, st7l35, st7l38, st7l39 supply, reset and clock management doc id 11928 rev 7 45/236 figure 16. reset block diagram 1. see section 12.2.2: illegal opcode reset on page 177 for more details on illegal opcode reset conditions the reset pin is an asynchronous sign al which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in section 13: electrical characteristics . 7.5.3 external power-on reset if the lvd is disabled by the option byte, to start up the microcontroller correctly, the user must use an external reset circuit to ensure that the reset signal is held low until v dd is over the minimum level specif ied for the selected f osc frequency. a proper reset signal for a slow rising v dd supply can generally be provided by an external rc network connected to the reset pin. 7.5.4 internal low voltage detector (lvd) reset two different reset sequences caused by the internal lvd circuitry can be distinguished: power-on reset voltage drop reset the device reset pin acts as an output that is pulled low when v dd supply, reset and clock management st7l34, st7l35, st7l38, st7l39 46/236 doc id 11928 rev 7 figure 17. reset sequences 7.6 system integrity management (si) the system integrity management block contains the low voltage detector (lvd) and auxiliary voltage detector (a vd) functions. it is mana ged by the sicsr register. note: a reset can also be triggered following the detection of an illegal op code or prebyte code. refer to section 12.2.2: illegal opcode reset on page 177 for further details. 7.6.1 low voltage detector (lvd) the low voltage detector (lvd) function generates a static reset when the v dd supply voltage is below a v it-(lvd) reference value. this means that it secures the power-up as well as the power-down, keeping the st7 in reset. the v it-(lvd) reference value for a voltage drop is lower than the v it+(lvd) reference value for power-on to avoid a parasitic reset when the mcu starts running and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: ?v it+(lvd) when v dd is rising ?v it-(lvd) when v dd is falling the lvd function is illustrated in figure 18: low voltage detector vs reset on page 47 . the lvd can be enabled by option byte with highest voltage threshold. v dd run reset pin external watchdog active phase v it+(lvd) v it-(lvd) t h(rstl)in run watchdog underflow t w(rstl)out run run reset reset source external reset lv d reset watchdog reset internal reset (256 or 4096 t cpu ) vector fetch active phase active phase
st7l34, st7l35, st7l38, st7l39 supply, reset and clock management doc id 11928 rev 7 47/236 provided the minimum v dd value (guaranteed for the osc illator frequency) is above v it-(lvd) , the mcu can only be in two modes: ? under full software control ? in static safe reset in these conditions, secure operation is always ensured for the application without the need for external reset hardware. during a low voltage detector reset, the reset pin is held low, thus permitting the mcu to reset other devices. note: 1 the lvd allows the device to be used without any external reset circuitry. 2 the lvd is an optional function which can be selected by the option byte. 3 use of lvd with capacitive power supply: with th is type of power supply, if power cuts occur in the application, it is recommended to pull v dd down to 0 v to ensure optimum restart conditions. refer to the circuit example in figure 98: reset pin prot ection when lvd is enabled on page 208 and note on the same page. 4 for the application to function correctly, it is recommended to make sure that the v dd supply voltage rises monotonously when the device is exiting from reset, to ensure the application functions properly . figure 18. low voltage detector vs reset v dd v it+(lvd) reset v it-(lvd) v hys
supply, reset and clock management st7l34, st7l35, st7l38, st7l39 48/236 doc id 11928 rev 7 figure 19. reset and supply management block diagram 7.6.2 low power modes 7.6.3 interrupts the avd interrupt event generates an interrupt if the corresponding enable control bit (avdie) is set and the interrupt mask in the cc register is reset (rim instruction). auxiliary voltage detector ( avd ) the voltage detector function (avd) is ba sed on an analog comparison between a v it-(avd) and v it+(avd) reference value and the v dd main supply voltage (v avd ). the v it-(avd) reference value for falling voltage is lower than the v it+(avd) reference value for rising voltage in order to avoid parasitic detection (hysteresis). the output of the avd comparator is directly readable by the application software through a real time status bit (avdf) in the sicsr register. this bit is read only. caution: the avd functions only if the lvd is enabled through the option byte. low voltage detector (lvd) auxiliary voltage detector (avd) reset v ss v dd reset sequence manager (rsm) avd interrupt request system integrity management watchdog timer sicsr (wdg) status flag av df lv drf loc ked wd grf av die table 11. effect of low power modes on system integrity mode description wait no effect on si. avd interrupts caus e the device to exit from wait mode. halt the sicsr register is frozen. the avd becomes inactive and the avd interrupt cannot be used to exit from halt mode. table 12. supply, reset and clock management interrupt control/wake-up capability interrupt event event flag enable cont rol bit exit from wait exit from halt avd event avdf avdie yes no
st7l34, st7l35, st7l38, st7l39 supply, reset and clock management doc id 11928 rev 7 49/236 monitoring the v dd main supply the avd voltage threshold value is relative to the selected lvd threshold configured by option byte (see section 15.2 on page 217 ). if the avd interrupt is enabled, an interrupt is generated when the voltage crosses the v it+(lvd) or v it-(avd) threshold (avdf bit is set). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcontroller. see figure 20 . figure 20. using the avd to monitor v dd 7.6.4 register description system integrity (si) control/status register (sicsr) v dd v it+(avd) v it-(avd) avdf bit 01 reset avdie bit = 1 v hyst avd interrupt request if interrupt cleared by hardware v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not yet in reset) 0 1 interrupt cleared by reset sicsr reset value: 0110 0xx0 (6xh) 76543210 reserved cr[1:0] wdgrf locked lvdrf avdf avdie - r/w r/w r/w r/w r/w r/w table 13. sicsr register description bit bit name function 7 - reserved, must be kept cleared 6:5 cr[1:0] rc oscillator frequency adjustment bits these bits, as well as cr[9:2] bits in the rccr register must be written immediately after reset to adjust the rc oscillator frequency and to obtain an accuracy of 1%. refer to section 7.3: register description on page 40
supply, reset and clock management st7l34, st7l35, st7l38, st7l39 50/236 doc id 11928 rev 7 4 wdgrf watchdog reset flag this bit indicates that the last reset was generated by the watchdog peripheral. it is set by hardware (watchdog reset) and cleared by software (by reading sicsr register) or an lvd reset (to ensure a stable cleared state of the wdgrf flag when cpu starts). combined with the lvdrf flag information, the flag description is given as follows: 00 (lvdrf, wdgrf): reset sources = external reset pin 01 (lvdrf, wdgrf): reset sources = watchdog 1x (lvdrf, wdgrf): reset sources = lvd 3locked pll locked flag this bit is set and cleared by hardware. it is set automatically when the pll reaches its operating frequency. 0: pll not locked 1: pll locked 2 lvdrf lv d r e s e t f l a g this bit indicates that the last reset was generated by the lvd block. it is set by hardware(lvd reset) and cleared by software (by reading). when the lvd is disabled by option byte, the lvdrf bit value is undefined. note: the lvdrf flag is not cleared when another reset type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the original failure. in this case, a watchdog reset can be detected by software while an external reset can not. 1avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is generated when the avdf bit is set. refer to figure 20 and to monitoring the vdd main supply on page 49 for additional details. 0: v dd over avd threshold 1: v dd under avd threshold 0avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag is set. the pending interrupt information is automatically cleared when software enters the avd interrupt routine. 0: avd interrupt disabled 1: avd interrupt enabled table 13. sicsr register description (continued) bit bit name function
st7l34, st7l35, st7l38, st7l39 interrupts doc id 11928 rev 7 51/236 8 interrupts the st7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in table 14: interrupt mapping on page 54 and a non-maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 21: interrupt processing flowchart on page 53 . the maskable interrupts must be enabled by clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). note: after reset, all interrupts are disabled. when an interrupt has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. the i bit of the cc register is set to prevent additional interrupts. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to table 14: interrupt mapping for vector addresses). the interrupt service routine should finish with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit is cleared and the main program resumes. priority management by default, a servicing interrupt cannot be interrupted because the i bit is set by hardware entering in interrupt routine. in the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see table 14: interrupt mapping ). interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specifically mentioned interrupts allow the processor to leave the halt low power mode (refer to the ?exit from halt? column in table 14: interrupt mapping ). 8.1 non maskable software interrupt this interrupt is entered when the trap instruction is executed regardless of the state of the i bit. it is serviced according to the flowchart in figure 21: interrupt processing flowchart on page 53 .
interrupts st7l34, st7l35, st7l38, st7l39 52/236 doc id 11928 rev 7 8.2 external interrupts external interrupt vectors can be loaded into th e pc register if the corresponding external interrupt occurred and if the i bit is cleared. these interrupts allow the processor to leave the halt low power mode. the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). an external interrupt triggered on edge will be latched and th e interrupt request automatically cleared upon entering the interrupt service routine. caution: the type of sensitivity defined in the miscellaneous or interrupt register (if available) applies to the ei source. in case of a nanded source (as described in section 10: i/o ports ), a low level on an i/o pin, configured as input with interrupt, masks the interrupt request even in case of rising-edge sensitivity. 8.3 peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both the following conditions are met: the i bit of the cc register is cleared the corresponding enable bit is set in the control register if either of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: writing ?0? to the corresponding bit in the status register or access to the status register while the flag is set followed by a read or write of an associated register. note: the clearing sequence resets the internal latch. a pending interrupt (that is, waiting for being enabled) will therefor e be lost if the clear sequence is executed.
st7l34, st7l35, st7l38, st7l39 interrupts doc id 11928 rev 7 53/236 figure 21. interrupt processing flowchart i bit set? y n iret? y n from reset load pc from interrupt vector stack pc, x, a, cc setibit fetch next instruction execute instruction this clears i bit by default restore pc, x, a, cc from stack interrupt y n pending?
interrupts st7l34, st7l35, st7l38, st7l39 54/236 doc id 11928 rev 7 table 14. interrupt mapping no. source block description register label priority order exit from halt or awufh address vector reset reset - highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 awu auto wakeup interrupt awucsr yes (1) fffah-fffbh 1 ei0 external interrupt 0 -yes fff8h-fff9h 2 ei1 external interrupt 1 fff6h-fff7h 3 ei2 external interrupt 2 fff4h-fff5h 4 ei3 external interrupt 3 fff2h-fff3h 5 lite timer lite timer rtc2 interrupt ltcsr2 no fff0h-fff1h 6 linsci linsci interrupt scicr1/ scicr2 no ffeeh-ffefh 7 si avd interrupt sicsr no ffech-ffedh 8 at timer at timer output compare interrupt or input capture interrupt pwmxcsr or atcsr no ffeah-ffebh 9 at timer overflow interrupt atcsr yes (2) ffe8h-ffe9h 10 lite timer lite timer input capture interrupt ltcsr no ffe6h-ffe7h 11 lite timer rtc1 interrupt ltcsr yes (2) ffe4h-ffe5h 12 spi spi peripheral interrupts spicsr yes ffe2h-ffe3h 13 at timer at timer overflow interrupt 2 atcsr2 no ffe0h-ffe1h 1. this interrupt exits the mcu from ?auto wakeup from halt? mode only 2. these interrupts exit the mcu from ?active halt? mode only
st7l34, st7l35, st7l38, st7l39 interrupts doc id 11928 rev 7 55/236 external interrupt control register (eicr) note: 1 these 8 bits can be written only when the i bit in the cc register is set. eicr reset value: 0000 0000 (00h) 76543210 is3[1:0] is2[1:0] is1[1:0] is0[1:0] r/w r/w r/w r/w table 15. eicr register description bit bit name function 7:6 is3[1:0] ei3 sensitivity these bits define the interrupt sensitivity for ei3 (port b0) according to ta bl e 1 6 5:4 is2[1:0] ei2 sensitivity these bits define the interrupt sensitivity for ei2 (port b3) according to ta bl e 1 6 3:2 is1[1:0] ei1 sensitivity these bits define the interrupt sensitivity for ei1 (port a7) according to ta bl e 1 6 1:0 is0[1:0] ei0 sensitivity these bits define the interrupt sensitivity for ei0 (port a0) according to ta bl e 1 6 table 16. interrupt sensitivity bits isx1 isx0 external interrupt sensitivity 0 0 falling edge and low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge
interrupts st7l34, st7l35, st7l38, st7l39 56/236 doc id 11928 rev 7 external interrupt selection register (eisr) eisr reset value: 0000 0000 (00h) 76543210 ei3[1:0] ei2[1:0] ei1[1:0] ei0[1:0] r/w r/w r/w r/w table 17. eisr register description bit bit name function 7:6 ei3[1:0] ei3 pin selection these bits are written by software. they select the port b i/o pin used for the ei3 external interrupt as follows: 00: i/o pin = no in terrupt (reset state) 01: i/o pin = pb0 10: i/o pin = pb1 11: i/o pin = pb2 5:4 ei2[1:0] ei2 pin selection these bits are written by software. they select the port b i/o pin used for the ei2 external interrupt as follows: 00: i/o pin = no in terrupt (reset state) 01: i/o pin = pb3 10: i/o pin = pb5 11: i/o pin = pb6 3:2 ei1[1:0] ei1 pin selection these bits are written by software. they select the port a i/o pin used for the ei1 external interrupt as follows: 00: i/o pin = no in terrupt (reset state) 01: i/o pin = pa4 10: i/o pin = pa5 11: i/o pin = pa6 1:0 ei0[1:0] ei0 pin selection these bits are written by software. they select the port a i/o pin used for the ei0 external interrupt as follows: 00: i/o pin = no interrupt (reset state)pa0 (reset state) 01: i/o pin = pa1 10: i/o pin = pa2 11: i/o pin = pa3
st7l34, st7l35, st7l38, st7l39 power saving modes doc id 11928 rev 7 57/236 9 power saving modes 9.1 introduction to give a large measure of flexibility to the ap plication in terms of power consumption, five main power saving modes are implemented in the st7 (see figure 22 ): slow wait (and slow-wait) active halt auto wakeup from halt (awufh) halt after a reset, the normal operating mode is selected by default (run mode). this mode drives the device (cpu and embedded periphera ls) by means of a master clock which is based on the main osc illator frequency divided or multiplied by 2 (f osc2 ). from run mode, the different power saving modes can be selected by setting the relevant register bits or by calling the specific st7 software instructi on whose action depends on the oscillator status. figure 22. power saving mode transitions power consumption wait slow run active halt high low slow wait auto wakeup from halt halt
power saving modes st7l34, st7l35, st7l38, st7l39 58/236 doc id 11928 rev 7 9.2 slow mode this mode has two targets: to reduce power consumption by decreasing the internal clock in the device to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by the sms bit in the mccsr register which enables or disables slow mode. in this mode, the oscillator fr equency is divided by 32. the cpu and peripherals are clocked at this lower frequency. note: slow-wait mode is activated when entering wa it mode while the device is already in slow mode. figure 23. slow mode clock transition sms f cpu normal run mode request f osc f osc /32 f osc
st7l34, st7l35, st7l38, st7l39 power saving modes doc id 11928 rev 7 59/236 9.3 wait mode wait mode places the mcu in a low power consumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. during wait mode, the i bit of the cc register is cleared to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until a reset or an interrupt occurs, causing it to wake up. then the program counter branches to the starting address of the interrupt or reset service routine. refer to figure 24: wait mode flowchart . figure 24. wait mode flowchart 1. before servicing an interrupt, the cc register is pus hed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals ibit on on 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off 0 on cpu oscillator peripherals ibit on on x (1) on cycle delay 256 or 4096 cpu clock
power saving modes st7l34, st7l35, st7l38, st7l39 60/236 doc id 11928 rev 7 9.4 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the ?halt? instruction when active halt is disabled (see section 9.5: active halt mode on page 62 for more details) and when the awuen bit in the awucsr register is cleared. the mcu can exit halt mode on reception of either a specific interrupt (see table 14: interrupt mapping on page 54 ) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is im mediately turned on and the 256 or 4096 cpu cycle delay is used to stabilize the oscillator. after the startup delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 26: halt mode flowchart on page 61 ). when entering halt mode, the i bit in the cc register is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in halt mode, the main oscillator is turned off, stopping all in ternal processing, including the operation of the on-chip peripherals. all pe ripherals are not clocked except those which receive their clock supply from another clock generator (such as an external or auxiliary oscillator). the compatibility of wa tchdog operati on with halt mode is configured by the ?wdghalt? option bit of the option byte. the halt instruction, when executed while the watchdog system is enabled, can generate a watchdog reset (see section 15.2: option bytes on page 217 for more details). figure 25. halt timing overview halt run run 256 or 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [active halt disabled]
st7l34, st7l35, st7l38, st7l39 power saving modes doc id 11928 rev 7 61/236 figure 26. halt mode flowchart 1. wdghalt is an option bit. see option byte section for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). refer to table 14: interrupt mapping on page 54 for more details. 4. before servicing an interrupt, the cc register is pus hed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. 5. if the pll is enabled by option byte, it outputs the clock after a delay of t startup (see figure 12 on page 39 ). reset interrupt (3) y n n y cpu oscillator peripherals (2) ibit off off 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off x (4) on cpu oscillator peripherals ibit on on x (4) on 256 or 4096 cpu clock watchdog enable disable wdghalt (1) 0 watchdog reset 1 halt instruction (active halt disabled) (awucsr.awuen=0) cycle delays (5)
power saving modes st7l34, st7l35, st7l38, st7l39 62/236 doc id 11928 rev 7 9.4.1 halt mode recommendations make sure that an external event is available to wake up the microcontroller from halt mode. when using an external interrupt to wake up the microcontroller, re-initialize the corresponding i/o as ?input pull-up with interrupt? or ?floating interrupt? before executing the halt instruction. the main reason fo r this is that the i/o may be incorrectly configured due to external interference or by an unforeseen logical condition. for the same reason, re-initialize the level sensitiveness of each external interrupt as a precautionary measure. the opcode for the halt instruction is 0x8e . to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memory. for example, avoid defi ning a constant in program memory with the value 0x8e. as the halt instruction clears the interrupt ma sk in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wakeup event (reset or external interrupt). 9.5 active halt mode active halt mode is the lowest power consumption mode of the mcu with a real-time clock (rtc) available. it is entered by executing the ?halt? instruction. the decision to enter either in active halt or halt mode is given by the ltcsr/atcsr register status as shown in the following table: the mcu exits in active halt mode on reception of a specific interrupt (see ta bl e 1 4 : interrupt mapping on page 54 ) or a reset. when exiting active halt mode by mean s of a reset, a 256 cpu cycle delay occurs. after the startup delay, the cpu resumes operation by fetching the reset vector which woke it up (see figure 28: active halt mode flowchart on page 63 ). when exiting active halt mode by means of an interrupt, the cpu immediately resumes operation by servicing the interrupt vector which woke it up (see figure 28: active halt mode flowchart on page 63 ). when entering active halt mode, the i bit in the cc register is cleared to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately (see figure 28 , note 2 ). table 18. ltcsr/atcsr register status ltcsr1 tb1ie bit atcsr ovfie bit atcsrck1 bit atcsrck0 bit meaning 0xx0 active halt mode disabled 00xx 1xxx active halt mode enabled x101
st7l34, st7l35, st7l38, st7l39 power saving modes doc id 11928 rev 7 63/236 in active halt mode, only the main oscilla tor and the selected time r counter (lt/at) are running to keep a wakeup time base. all other peripherals are not clocked except those which receive their clock supply from another clock generator (such as external or auxiliary oscillator). note: as soon as active halt is enabled, executing a halt instruction while the watchdog is active does not generate a reset. this means that the device cannot exceed a defined delay in this power saving mode. figure 27. active halt timing overview 1. this delay occurs only if the mcu exit s active halt mode by means of a reset. figure 28. active halt mode flowchart 1. peripherals clocked with an external clock source can still be active. 2. only the rtc1 interrupt and some specific interrupt s can exit the mcu from ac tive halt mode. refer to table 14: interrupt mapping for more details. 3. before servicing an interrupt, the cc register is pus hed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. halt run run 256 or 4096 cpu cycle delay (1) reset or interrupt halt instruction fetch vector [active halt enabled] active halt instruction reset interrupt (2) y n n y cpu oscillator peripherals (1) ibit on off 0 off fetch reset vector or service interrupt cpu oscillator peripherals (1) ibit on off x (3) on cpu oscillator peripherals ibit on on x (3) on 256 or 4096 cpu clock (active halt enabled) (awucsr.awuen = 0) cycle delay
power saving modes st7l34, st7l35, st7l38, st7l39 64/236 doc id 11928 rev 7 9.6 auto wakeup from halt mode auto wakeup from halt (awufh) mode is similar to halt mode with the addition of a specific internal rc oscillator for wakeup (auto wakeup fr om halt oscillator). comp ared to active halt mode, awufh has lower power consumption (the main clock is not kept running but there is no accurate real-time clock available). it is entered by executing the halt inst ruction when the awuen bit in the awucsr register has been set. figure 29. awufh mode block diagram as soon as halt mode is entered and if the awuen bit has been set in the awucsr register, the awu rc oscillator provides a clock signal (f awu_rc ). its frequency is divided by a fixed divider and a programmable prescaler controlled by the awupr register. the output of this prescaler provides the delay time. when the delay has elapsed, the awuf flag is set by hardware and an interrupt wakes up the mcu from halt mode. at the same time, the main oscillator is immediately turned on and a 256 c ycle delay is used to stabilize it. after this startup delay, the cpu resumes operation by servicing the awufh interrupt. the awu flag and its associated interrupt are cleared by software reading the awucsr register. to compensate for any frequency dispersion of the awu rc oscillator, it can be calibrated by measuring the clock frequency f awu_rc and then calculating the right prescaler value. measurement mode is enabled by setting the awum bit in the awucsr register in run mode. this connects f awu_rc to the input capture of the 12-bit autoreload timer, allowing the f awu_rc to be measured using the main oscillator clock as a reference timebase. awu rc oscillator awufh f awu_rc awufh interrupt (ei0 source) prescaler/1 .. 255 /64 divider to autoreload timer input capture 1 0 awuck opt bit 32 khz oscillator
st7l34, st7l35, st7l38, st7l39 power saving modes doc id 11928 rev 7 65/236 similarities with halt mode the following awufh mode behavior is the same as normal halt mode: the mcu can exit awufh mode by means of any inte rrupt with exit from halt capability or a reset (see section 9.4: halt mode on page 60 ). when entering awufh mode, the i bit in the cc register is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in awufh mode, the main oscillator is turned off, stopping all in ternal processing, including the operation of the on-chip peripherals. none of the peripherals are clocked except those which receive their clock supply from another clock generator (suc h as an external or auxiliary oscillator like the awu oscillator). the compatibility of watchdog oper ation with awufh mode is conf igured by the wdghalt option bit in the option byte. depending on this setting, the halt instruction, when executed while the watchdog system is enabled, can generate a watchdog reset. figure 30. awuf halt timing diagram awufh interrupt f cpu run mode halt mode 256 or 4096 tcpu run mode f awu_rc clear by software t awu
power saving modes st7l34, st7l35, st7l38, st7l39 66/236 doc id 11928 rev 7 figure 31. awufh mode flowchart 1. wdghalt is an option bit. see section 15.2: option bytes on page 217 for more details. 2. peripheral clocked with an external clock source can still be active. 3. only an awufh interrupt and some specific interrupt s can exit the mcu from halt mode (such as external interrupt). refer to table 14: interrupt mapping on page 54 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and recovered when the cc register is popped. 5. if the pll is enabled by the option byte, it out puts the clock after an additional delay of t startup (see figure 12: pll output frequen cy timing diagram on page 39 ). reset interrupt( 3) y n n y cpu main osc peripherals (2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu main osc peripherals i[1:0] bits on off xx( 4) on cpu main osc peripherals i[1:0] bits on on xx (4) on 256 or 4096 cpu clock cycle delay (5) watchdog enable disable wdghalt (1) 0 watchdog reset 1 awu rc osc on awu rc osc off awu rc osc off halt instruction (active halt disabled) (awucsr.awuen = 1)
st7l34, st7l35, st7l38, st7l39 power saving modes doc id 11928 rev 7 67/236 register description awufh control/status register (awucsr) awucsr reset value: 0000 0000 (00h) 76543210 reserved reserved reserved reserved reserved awuf awum awuen -----r/wr/wr/w table 19. awucsr register description bit bit name function 7:3 - reserved, must be kept cleared 2awuf auto wakeup flag this bit is set by hardware when the awu module generates an interrupt and cleared by software on reading awucsr. writing to this bit does not change its value. 0: no awu interrupt occurred 1: awu interrupt occurred 1awum auto wakeup measurement this bit enables the awu rc oscillat or and connects its output to the input capture of the 12-bi t autoreload timer. this allows the timer to measure the awu rc oscillator dispersion and then compensate this dispersion by providing the right value in the awupr register. 0: measurement disabled 1: measurement enabled 0awuen auto wakeup from halt enabled this bit enables the auto wakeup from halt feature: once halt mode is entered, the awufh wakes up the microcontroller after a time delay dependent on the awu prescaler value. it is set and cleared by software. 0: awufh (auto wakeup from halt) mode disabled 1: awufh (auto wakeup from halt) mode enabled
power saving modes st7l34, st7l35, st7l38, st7l39 68/236 doc id 11928 rev 7 awufh prescaler register (awupr) in awu mode, the period that the mcu stays in halt mode (t awu in figure 30: awuf halt timing diagram on page 65 ) is definedby this prescaler register can be programmed to modify the time that the mcu stays in halt mode before waking up automatically. note: if 00h is written to awupr, depending on th e product, an interrupt is generated immediately after a halt instruction or the awupr remains unchanged. awupr reset value: 1111 1111 (ffh) 76543210 awupr[7:0] r/w table 20. awupr register description bit bit name function 7:0 awupr[7:0] auto wakeup prescaler these 8 bits define the awupr dividing factor as explained in ta b l e 2 1 table 21. awupr dividing factor awupr[7:0 ] dividing factor 00h forbidden 01h 1 ... ... feh 254 ffh 255 table 22. awu register map and reset values address (hex.) register label 76543210 0049h awupr reset value awupr7 1 awupr6 1 awupr5 1 awupr4 1 awupr3 1 awupr2 1 awupr1 1 awupr0 1 004ah awucsr reset value 0 0 0 0 0 awuf awum awuen t awu 64 awupr 1 f awurc ------------------------- -t rcstrt + =
st7l34, st7l35, st7l38, st7l39 i/o ports doc id 11928 rev 7 69/236 10 i/o ports 10.1 introduction the i/o ports allow data transfer. an i/o port contains up to eight pins. each pin can be programmed independently either as a digital input or digital output. in addition, specific pins may have several other functions. these functions can include external interrupt, alternate signal input/output for on-chip peripherals or analog input. 10.2 functional description a data register (dr) and a data direction register (ddr) are always associated with each port. the option register (or), which allows input/output options, may or may not be implemented. the following description takes into account the or register. refer to section 10.7: device-specific i/o port configuration on page 74 for device specific information. an i/o pin is programmed using the corresponding bits in the ddr, dr and or registers: bit x corresponding to pin x of the port. figure 32: i/o port general block diagram on page 71 shows the generic i/o block diagram. 10.2.1 input modes clearing the ddrx bit selects input mode. in this mode, reading its dr bit returns the digital value from that i/o pin. if an or bit is available, different input modes can be configured by software: floating or pull-up. refer to section 10.3: i/o port implementation on page 73 for configuration. note: 1 writing to the dr modifies the latch value but does not change the state of the input pin. 2 do not use read/modify/write instructions (bset/bres) to modify the dr register. external interrupt function depending on the device, setting the orx bit while in input mode can configure an i/o as an input with interrupt. in this configuration, a signal edge or level input on the i/o generates an interrupt request via the correspo nding interrupt vector (eix).fa lling or rising edge sensitivity is programmed independently for each interrupt vector. the external interrupt control register (eicr) or the miscellaneous register controls this sensitivity, depending on the device. each external interrupt vector is linked to a dedicated group of i/o port pins (see pinout description in section 2: pin description on page 16 and interrupt section).if several i/o interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. for this reason, if one of the interrupt pins is tied low, it may mask the others. external interrupts are hardware interrupts. fetching the corresponding interrupt vector automatically clears the request latch. changing the sensitivity bits clears any pending interrupts.
i/o ports st7l34, st7l35, st7l38, st7l39 70/236 doc id 11928 rev 7 10.2.2 output modes setting the ddrx bit selects output mode. writing to the dr bits applies a digital value to the i/o through the latch. reading the dr bits returns the previously stored value. if an or bit is available, different output modes can be selected by software: push-pull or open-drain. refer to section 10.3: i/o port implementation on page 73 for configuration. 10.2.3 alternate functions many st7 i/os have one or more alternate functions. these may include output signals from, or input signals to, on-chip peripherals. table 2: device pin description on page 17 describes which peripheral signals can be input/output to which ports. a signal coming from an on-chip peripheral can be output on an i/o. to do this, enable the on-chip peripheral as an output (enable bit in the peripheral?s control register). the peripheral configures the i/o as an output and takes priority over standard i/o programming. the i/o?s state is readable by addressing the corresponding i/o data register. configuring an i/o as floating enables alternate function input. it is not recommended to configure an i/o as pull-up as this increases current consumption. before using an i/o as an alternate input, configure it without interrupt. otherwise spurious interrupts can occur. configure an i/o as input floating for an on-chip peripheral signal which can be input and output. caution: i/os which can be configured as both an analog and digital alternate function need special attention. the user must control the peripherals so that the signals do not arrive at the same time on the same pin. if an external clock is used, only the clock alternate function should be employed on that i/o pin and not the other alternate function. table 23. dr value and output pin status dr push-pull open-drain 0v ol v ol 1v oh floating
st7l34, st7l35, st7l38, st7l39 i/o ports doc id 11928 rev 7 71/236 figure 32. i/o port general block diagram table 24. i/o port mode options (1) 1. legend: off = implemented not activated; on = implemented and activated configuration mode pull-up p-buffer diodes to v dd (2) 2. the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ol is implemented to protect the device against positive stress. to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (3) 3. for further details on port configuration, please refer to table 28: port configuration (standard ports) and table 29: port configuration (external interrupts) on page 74 . dr ddr or data bus pad v dd alternate enable bit alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external request (eix) interrupt sensitivity selection cmos schmitt trigger register access from on-chip peripheral to on-chip peripheral combinational logic t
i/o ports st7l34, st7l35, st7l38, st7l39 72/236 doc id 11928 rev 7 analog alternate function configure the i/o as floating input to use an adc input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the adc input. table 25. i/o configuration hardware configuration input (1) 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read th e alternate function output status. open-drain output (2) 2. when the i/o port is in output configuration and t he associated alternate func tion is enabled as an input, the alternate function reads the pin stat us given by the dr register content. 3. for true open drain, these elements are not implemented push-pull output (2) note 3 pad v dd r pu dr register access w r dr register pull-up condition alternate input to on-chip peripheral external interrupt source (ei x ) combinational logic polarity selection interrupt condition from other pins data bus analog input note 3 pad r pu r/w v dd dr register access dr register data bus pad r/w note 3 dr register access data bus dr register v dd r pu alternate enable bit alternate output from on-chip peripheral
st7l34, st7l35, st7l38, st7l39 i/o ports doc id 11928 rev 7 73/236 analog recommendations do not change the voltage level or loading on any i/o while conversion is in progress. do not have clocking pins located close to a selected analog pin. warning: the analog input voltage level must be within the limits stated in the absolute maximum ratings. 10.3 i/o port implementation the hardware implementation on each i/o port depends on the settings in the ddr and or registers and specific i/o port features such as adc input or open drain. switching these i/o ports from one state to another should be done in a sequence that prevents unwanted side effects. recommend ed safe transitions are illustrated in figure 33 . other transitions are potentially risky and s hould be avoided, since they may present unwanted side-effects such as spurious interrupt generation. figure 33. interrupt i/o port state transitions 10.4 unused i/o pins unused i/o pins must be connected to fixed voltage levels. refer to section 13.8: i/o port pin characteristics on page 201 . 10.5 low-power modes 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx =ddr, or table 26. effect of low power modes on i/o ports mode description wait no effect on i/o ports. external interrup ts cause the device to exit from wait mode. halt no effect on i/o ports. external interrup ts cause the device to exit from halt mode.
i/o ports st7l34, st7l35, st7l38, st7l39 74/236 doc id 11928 rev 7 10.6 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and if the i bit in the cc register is cleared (rim instruction). related documentation spi communication between st7 and eeprom (an970) s/w implementation of i 2 c bus master (an1045) software lcd driver (an1048) 10.7 device-specific i/o port configuration the i/o port register configurations are summarized as follows: on ports where the external interrupt capabilit y is selected using th e eisr register, the configuration is as follows: table 27. i/o interrupt control/wake-up capability interrupt event event flag enable contro l bit exit from wait exit from halt external interrupt on selected external event - ddrx orx ye s ye s table 28. port configuration (standard ports) port pin name input (ddr = 0) output (ddr = 1) or = 0 or = 1 or = 0 or = 1 port a pa7:0 floating pull-up open drain push-pull port b pb6:0 table 29. port configuration (external interrupts) port pin name input with interrupt (ddr = 0 ; eisr 00) or = 0 or = 1 port a pa6:1 floating pull-up port b pb5:0 table 30. i/o port register map and reset values address(hex.) register label 7 654321 0 0000h pa d r reset value msb 1 111111 lsb 1 0001h paddr reset value msb 0 000000 lsb 0
st7l34, st7l35, st7l38, st7l39 i/o ports doc id 11928 rev 7 75/236 0002h pao r reset value msb 0 100000 lsb 0 0003h pbdr reset value msb 1 111111 lsb 1 0004h pbddr reset value msb 0 000000 lsb 0 0005h pbor reset value msb 0 000000 lsb 0 table 30. i/o port register map and reset values (continued) address(hex.) register label 7 654321 0
on-chip peripherals st7l34, st7l35, st7l38, st7l39 76/236 doc id 11928 rev 7 11 on-chip peripherals 11.1 watchdog timer (wdg) 11.1.1 introduction the watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen lo gical conditions, which causes the application program to abandon its normal sequence. the watchdog circuit generates an mcu reset upon expiration of a programmed time period, unless the program refreshes the counter?s contents before the t6 bit is cleared. 11.1.2 main features programmable free-running downcounter (64 increments of 16000 cpu cycles) programmable reset reset (if watchdog activated) when the t6 bit reaches zero optional reset on halt instruction (configurable by option byte) hardware watchdog selectable by option byte 11.1.3 functional description the counter value stored in the cr register (bits t[6:0]) is decremented every 16000 machine cycles and the length of thetimeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 become s cleared), it initiates a rese t cycle pulling low the reset pin for typically 30 s. figure 34. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider 16000 watchdog control register (cr) t1 t2 t3 t4 t5
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 77/236 the application program must write in the cr register at regular intervals during normal operation to prevent an mcu reset. this downcounter is free-running: it counts down, even if the watchdog is disabled. the value to be stored in the cr register must be between ffh and c0h (see ta b l e 3 1 ): the wdga bit is set (watchdog enabled) the t6 bit is set to prevent generating an immediate reset the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. following a reset, the watchdog is disabled. once activated, it can be disabled only by a reset. the t6 bit can generate a software reset (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction generates a reset. . 11.1.4 hardware watchdog option if hardware watchdog is selected by the option byte, the watchdog is always active and the wdga bit in the cr is not used. refer to the option byte description in section 15.2: option bytes on page 217 . using halt mode with the wdg (wdghalt option) if halt mode with watchdog is enabled by the option byte (no watchdog reset on halt instruction), it is recommended before executing the halt instruction to refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcontroller. 11.1.5 interrupts none. table 31. watchdog timing (1) 1. the timing variation shown in table 31 is due to the unknown status of the prescaler when writing to the cr register. f cpu = 8 mhz wdg counter code min (ms) max (ms) c0h 1 2 ffh 127 128
on-chip peripherals st7l34, st7l35, st7l38, st7l39 78/236 doc id 11928 rev 7 11.1.6 register description watchdog control register (wdgcr) wdgcr reset value: 0111 1111 (7fh) 76543210 wdga t[6:0] r/w r/w table 32. wdgcr register description bit bit name function 7wdga activation bit (1) this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled 1. the wdga bit is not used if the hardw are watchdog option is enabled by option byte. 6:0 t[6:0] 7-bit counter (msb to lsb) these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). table 33. watchdog timer register map and reset values address (hex.)register label7 6543210 002eh wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 79/236 11.2 dual 12-bit auto reload timer 3 (at3) 11.2.1 introduction the 12-bit autoreload timer can be used for gene ral-purpose timing functions. it is based on one or two free-running 12-bit upcounters with an input capture register and four pwm output channels. there are six external pins: 4 pwm outputs atic/ltic pin for the input capture function break pin for forcing a break condition on the pwm outputs 11.2.2 main features single timer or dual timer mode with two 12-bit upcounters (cntr1/cntr2) and two 12-bit autoreload registers (atr1/atr2) maskable overflow interrupts pwm mode ? generation of four independent pwmx signals ? dead time generation for half-bridge driving mode with programmable dead time ? frequency 2 khz to 4 mhz (@ 8 mhz f cpu ) ? programmable duty-cycles ? polarity control ? programmable output modes output compare mode input capture mode ? 12-bit input capture register (aticr) ? triggered by risi ng and falling edges ? maskable ic interrupt ? long range input capture break control flexible clock control
on-chip peripherals st7l34, st7l35, st7l38, st7l39 80/236 doc id 11928 rev 7 figure 35. single time r mode (encntr2 = 0) figure 36. dual timer mode (encntr2 = 1) 11.2.3 functional description pwm mode this mode allows up to four pulse width modulated signals to be generated on the pwmx output pins. pwm frequency atic pwm0 pwm1 pwm2 pwm3 pwm3 duty cycle generator 12-bit input capture pwm2 duty cycle generator pwm1 duty cycle generator pwm0 duty cycle generator 12-bit autoreload register 1 12-bit upcounter 1 clock control 1ms f cpu edge detection circuit output compare cmp interrupt from lite timer ovf1 interrupt oe0 oe1 oe2 oe3 dead time generator dte bit bpen bit break function pwm0 pwm1 pwm2 pwm3 dead time generator pwm3 duty cycle generator 12-bit input capture 12-bit autoreload register 2 12-bit upcounter 2 pwm2 duty cycle generator pwm1 duty cycle generator pwm0 duty cycle generator 12-bit autoreload register 1 12-bit upcounter 1 clock control 1ms f cpu output compare cmp interrupt ovf1 interrupt ovf2 interrupt edge detection circuit oe0 oe1 oe2 oe3 atic dte bit bpen bit break function
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 81/236 the four pwm signals can have the same frequency (f pwm ) or can have two different frequencies. this is selected by the encntr2 bit which enables single timer or dual timer mode (see figure 35: single timer mode (encntr2 = 0) on page 80 and figure 36: dual timer mode (encntr2 = 1) on page 80 ). the frequency is controlled by the counter period and the atr register value. in dual timer mode, pwm2 and pwm3 can be generated with a different frequency controlled by cntr2 and atr2. following the above formula, if f counter is 4 mhz , the maximum value of f pwm is 2 mhz (atr register value = 4094), the minimum value is 1 khz (atr register value = 0). duty cycle the duty cycle is selected by programming the dcrx registers. these are preload registers. the dcrx values are transferred in active duty cycle registers after an overflow event if the corresponding transfer bit (tranx bit) is set. the tran1 bit controls the pwmx outputs driv en by counter 1 and the tran2 bit controls the pwmx outputs driven by counter 2. pwm generation and output compare are done by comparing these active dcrx values with the counter. the maximum available resolution for the pwmx duty cycle is: where atr is equal to 0. with this maximum resolution, 0% and 100% duty cycle can be obtained by changing the polarity. at reset, the counter starts counting from 0. when an upcounter overflow occurs (ovf event), the preloaded duty cycle values are transferred to the active duty cycle registers and the pwmx signals are set to a high level. when the upcounter matches the active dcrx value, the pwmx signals are set to a low level. to obtain a signal on a pwmx pin, the contents of the corresponding active dcrx register must be greater than the contents of the atr register. note: for rom devices only: the pwm can be enabled/disabled only in overflow isr, otherwise the first pulse of pwm can be different fr om expected one because no force overflow function is present. the maximum value of atr is 4094 because it mu st be lower than the dcr value, which in this case must be 4095. polarity inversion the polarity bits can be used to invert any of the four output signals. the inversion is synchronized with the counter overflow if the corresponding transfer bit in the atcsr2 register is set (reset value). see figure 37 . f pwm = f counter /(4096 - atr) resolution = 1/(4096 - atr)
on-chip peripherals st7l34, st7l35, st7l38, st7l39 82/236 doc id 11928 rev 7 figure 37. pwm polarity inversion the data flip flop (dff) applies the polarity inversion when triggered by the counter overflow input. output control the pwmx output signals can be enabled or disabled using the oex bits in the pwmcr register. figure 38. pwm function pwmx pwmx pin counter overflow opx pwmxcsr register inverter dff tranx atcsr2 register duty cycle register autoreload register pwmx output t 4095 000 with oe=1 and opx=0 (atr) (dcrx) with oe=1 and opx=1 counter
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 83/236 figure 39. pwm signal from 0% to 100%duty cycle dead time generation a dead time can be inserted between pwm0 and pwm1 using the dtgr register. this is required for half-bridge driving where pwm signals must not be overlapped. the non-overlapping pwm0/pwm1 signals are generated through a programmable dead time by setting the dte bit. dtgr[7:0] is buffered insi de so as to avoid deforming the curren t pwm cycle. the dtgr effect will take place only after an overflow. note: 1 dead time is generated only when dte = 1 and dt[6:0] 0 . if dte is set and dt[6:0] = 0, pwm output signals will be at their reset state. 2 half-bridge driving is possible only if polarities of pwm0 and pwm1 are not inverted, that is, if op0 and op1 are not set. if polarity is inverted, overlapping pw m0/pwm1 signals will be generated. counter pwmx output t with mod00=1 and opx=0 ffdh ffeh fffh ffdh ffeh fffh ffdh ffeh dcrx=000h dcrx=ffdh dcrx=ffeh dcrx=000h atr= ffdh f counter pwmx output with mod00=1 and opx=1 dead time value = dt[6:0] x tcounter1
on-chip peripherals st7l34, st7l35, st7l38, st7l39 84/236 doc id 11928 rev 7 figure 40. dead time generation in the above example, when the dte bit is set: pwm goes low at dcr0 match and goes high at atr1 + t dt pwm1 goes high at dcr0 + t dt and goes low at atr match. with this programmable delay (t dt ), the pwm0 and pwm1 signals which are generated are not overlapped. break function the break function can be used to perform an emergency shutdown of the application being driven by the pwm signals. the break function is activated by the external break pin (active low). in order to use the break pin it must be previously enabled by software setting the bpen bit in the breakcr register. when a low level is detected on the break pin, the ba bit is set and the break function is activated. in this case, the four pwm signals are stopped. software can set the ba bit to activate the break function without using the break pin. when a break function is activate d (ba bit = 1 and bren1/bren2 = 1): the break pattern (pwm [3:0] bits in the br eakcr is forced dire ctly on the pwmx output pins (after the inverter) the 12-bit pwm counter cntr1 is put to its reset value, that is, 00h the 12-bit pwm counter cntr2 is put to its reset value, that is 00h atr1, atr2, preload and active dcrx are put to their reset values the pwmcr register is reset counters stop counting dcr0+1 atr1 dcr0 t dt t dt t dt = dt[6:0] x t counter1 pwm 0 pwm 1 cntr1 ck_cntr1 t counter1 ovf pwm 0 pwm 1 if dte = 0 if dte = 1 counter = dcr0 counter = dcr1
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 85/236 when the break function is deactivated after ap plying the break (ba bit goes from 1 to 0 by software): the control of the four pwm outputs is transferred to the port registers. figure 41. block diagram of break function 1. the break pin value is latched by the ba bit pwm0 pwm1 pwm2 pwm3 1 0 pwm0 pwm1 pwm2 pwm3 breakcr register break pin pwm counter -> reset value atrx & dcrx -> reset value pwm mode -> reset value when ba is set: (active low) (inverters) pwm0 pwm1 pwm2 pwm3 bpen ba
on-chip peripherals st7l34, st7l35, st7l38, st7l39 86/236 doc id 11928 rev 7 output compare mode to use this function, load a 12-bit valu e in the preload dcrxh and dcrxl registers. when the 12-bit upcounter cntr1 reaches the value stored in the active dcrxh and dcrxl registers, the cmpfx bit in the pwmxcsr register is set and an interrupt request is generated if the cmpie bit is set. the output compare function is always performed on cntr1 in both single timer mode and dual timer mode and never on cntr2. the difference is that in single timer mode the counter 1 can be compared with any of the four dcr registers and in dual timer mode, the counter 1 is compar ed with dcr0 or dcr1. note: 1 the output compare function is only available for dcrx values other than 0 (reset value). 2 duty cycle registers are buffered internally. th e cpu writes in prelo ad duty cycle registers and these values are transferred to active duty cycle registers after an overflow event if the corresponding transfer bit (tran1 bit) is set. output compare is done by comparing these active dcrx values with the counter. figure 42. block diagram of output compare mode (single timer) dcrx output compare circuit counter 1 (atcsr) cmpie preload duty cycle regx active duty cycle regx cntr1 tran1 (atcsr2) ovf (atcsr) cmpfx (pwmxcsr) cmp interrupt request
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 87/236 input capture mode the 12-bit aticr register is used to latch the value of the 12-bit free running upcounter cntr1 after a rising or falling edge is detected on the atic pin. when an input capture occurs, the icf bit is set and the aticr register contains the value of the free running upcounter. an ic interrupt is generated if the icie bit is set. the icf bit is reset by reading the aticrh/aticrl register when the icf bit is set. the aticr is a read only register and always contains the free running upcounter value which corresponds to the most recent input capture. any further input capture is inhibited while the icf bit is set. figure 43. block diagram of input capture mode figure 44. input capture timing diagram at c s r ck0 ck1 icie icf 12-bit autoreload register 12-bit upcounter1 f cpu at i c 12-bit input capture register ic interrupt request at r 1 at i c r cntr1 f lt i m e r @ 8 mhz) (1 ms off timebase counter1 t 01h f counter xxh 02h 03h 04h 05h 06h 07h 04h atic pin icf flag interrupt 08h 09h 0ah interrupt aticr read 09h
on-chip peripherals st7l34, st7l35, st7l38, st7l39 88/236 doc id 11928 rev 7 long input capture pulses that last between 8 s and 2 s can be measured with an accuracy of 4s if f osc = 8 mhz under the following conditions: the 12-bit at3 timer is clocked by the lite ti mer (rtc pulse: ck[1:0] = 01 in the atcsr register) the ics bit in the atcsr2 register is set so that the ltic pin is used to trigger the at3 timer capture. the signal to be captured is connected to ltic pin input capture registers lticr, aticrh and aticrl are read this configuration allows to cascade the lite timer and the 12-bit at3 timer to get a 20-bit input capture value. refer to figure 45 . figure 45. long range input capture block diagram since the input capture flags (icf) for both timers (at3 timer and lt timer) are set when signal transition occurs, software must mask one interrupt by clearing the corresponding icie bit before setting the ics bit. if the ics bit changes (from 0 to 1 or from 1 to 0), a spurious transition might occur on the input capture signal because of different values on ltic and atic. to avoid this situation, it is recommended to do the following: first, reset both icie bits then set the ics bit reset both icf bits then set the icie bit of desired interrupt lt i c at i c ics 1 0 12-bit input capture register off f cpu f lt i m e r 12-bit upcounter1 12-bit autoreload register 8-bit input capture register 8-bit timebase counter1 f osc/32 lt i c r cntr1 at i c r at r 1 8 lsb bits 12 msb bits lite timer 12-bit artimer 20 cascaded bits
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 89/236 both timers are used to compute a pulse length with long input capture feature. the procedure is not straight-forward and is as follows: at the first input capture on the rising edge of the pulse, we assume that values in the registers are as follows: ? lticr = lt1 ? aticrh = ath1 ? aticrl = atl1 ? hence aticr1 [11:0] = ath1 & atl1 ? refer to figure 46 . at the second input capture on the falling edge of the pulse, we assume that the values in the registers are as follows: ? lticr = lt2 ? aticrh = ath2 ? aticrl = atl2 ? hence aticr2 [11:0] = ath2 & atl2 now pulse width p between first capture and second capture is: figure 46. long range input capture timing diagram 11.2.4 low power modes table 34. effect of low power modes on at3 timer mode description slow the input frequency is divided by 32 wait no effect on at timer p = decimal (f9 ? lt1 + lt2 + 1) * 0.004ms + decimal (aticr2 - aticr1 ? 1) * 1ms f9h 00h lt1 f9h 00h lt2 ath1 & atl1 00h 0h lt1 ath1 lt2 ath2 f osc/32 tb counter1 cntr1 ltic lticr aticrh 00h atl1 atl2 aticrl aticr = aticrh[3:0] & aticrl[7:0] _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ath2 & atl2 _ _ _
on-chip peripherals st7l34, st7l35, st7l38, st7l39 90/236 doc id 11928 rev 7 11.2.5 interrupts 11.2.6 register description timer control status register (atcsr) active halt at timer halted except if ck0 = 1, ck1 = 0 and ovfie = 1 halt at timer halted table 34. effect of low power modes on at3 timer (continued) table 35. at3 interrupt control/wake-up capability interrupt event (1) 1. the cmp and at3 ic events are connected to the same interrupt vector. the ovf event is mapped on a separate vector (see section 8: interrupts ). they generate an interrupt if the enable bit is set in the atcsr register and the interrupt mask in the cc register is reset (rim instruction). event flag enable control bit exit from wait exit from halt exit from active halt overflow event ovf1 ovfie1 ye s n o ye s (2) 2. only if ck0 = 1 and ck1 = 0 (f counter = f ltimer ) at3 ic event icf icie no cmp event cmpfx cmpie atcsr reset value: 0x00 0000 (x0h) 76543210 reserved icf icie ck[1:0] ovf1 ovfie1 cmpie - r/w r/w r/w r/w r/w r/w table 36. atcsr register description bit bit name function 7 - reserved, must be kept cleared 6icf input capture flag this bit is set by hardware and cleared by software by reading the aticr register (a read access to at icrh or aticrl clears this flag). writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred 5icie ic interrupt enable this bit is set and cleared by software. 0: input capture interrupt disabled 1: input capture interrupt enabled
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 91/236 counter register 1 high (cntr1h) counter register 1 low (cntr1l) 4:3 ck[1:0] counter clock selection these bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter as follows/ 00: counter clock selection = off 01: counter clock selection = f lt i m e r (1ms timebase @ 8 mhz) 10: counter clock selection = f cpu 11: counter clock selection = off 2ovf1 overflow flag this bit is set by hardware and cleared by software by reading the tcsr register. it indicates the tran sition of the counter1 cntr1 from ffh to atr1 value. 0: no counter overflow occurred 1: counter overflow occurred 1ovfie1 overflow interrupt enable this bit is read/writen by software and cleared by hardware after a reset. 0: overflow interrupt disabled 1: overflow interrupt enabled 0cmpie compare interrupt enable this bit is read/writen by software and cleared by hardware after a reset. it can be used to mask the interrupt generated when any of the cmpfx bit is set. 0: output compare interrupt disabled 1: output compare interrupt enabled cntr1h reset value: 0000 0000 (00h) 15 14 13 12 11 10 9 8 reserved reserved reserved reserved cntr1[11:8] ---- r cntr1l reset value: 0000 0000 (00h) 7654 3 2 1 0 cntr1[7:0] r table 36. atcsr register description (continued) bit bit name function
on-chip peripherals st7l34, st7l35, st7l38, st7l39 92/236 doc id 11928 rev 7 table 37. cntr1h and cntr1l register descriptions bit bit name function 15:12 - reserved, must be kept cleared 11:0 cntr1[11:0] counter value this 12-bit register is read by software and cleared by hardware after a reset. the counter cntr1 increm ents continuously as soon as a counter clock is selected. to obtain the 12-bit value, software should read the counter value in two consecutive read operations. the cntr1h register can be incremented between the two reads, and in order to be accurate when f timer =f cpu , the software should take this into account when cntr1l and cntr1h are read. if cntr1l is close to its highest value, cntr1h could be incremented before it is read. when a counter overflow occurs, the counter restarts from the value specified in the atr1 register.
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 93/236 autoreload register high (atr1h) autoreload register low (atr1l) pwm output control register (pwmcr) atr1h reset value: 0000 0000 (00h) 15 14 13 12 11 10 9 8 reserved reserved reserved reserved atr1[11:8] ---- r/w atr1l reset value: 0000 0000 (00h) 7654 3 2 1 0 atr1[7:0] r/w table 38. atr1h and atr1l register descriptions bit bit name function 15:12 - reserved, must be kept cleared 11:0 atr1[11:0] autoreload register 1 this is a 12-bit register which is written by software. the atr1 register value is automatically loaded into the upcounter cntr1 when an overflow occurs. the register value is used to set the pwm frequency. pwmcr reset value: 0000 0000 (00h) 76543210 reserved oe3 reserved oe2 reserved oe1 reserved oe0 - r/w - r/w - r/w - r/w table 39. pwmcr register description bit bit name function 7, 5, 3, 1 - reserved, must be kept cleared 6, 4, 2, 0 oe[3:0] pwmx output enable these bits are set and cleared by software and cleared by hardware after a reset. 0: pwm mode disabled. pwmx output alternate function disabled (i/o pin free for general purpose i/o) 1: pwm mode enabled
on-chip peripherals st7l34, st7l35, st7l38, st7l39 94/236 doc id 11928 rev 7 pwmx control status register (pwmxcsr) pwmxcsr reset value: 0000 0000 (00h) 76543210 reserved reserved reserved reserved reserved reserved opx cmpfx ----- -r/wr/w table 40. pwmxcsr register description bit bit name function 7:2 - reserved, must be kept cleared 1opx pwmx output polarity this bit is read/writen by software and cleared by hardware after a reset. this bit selects the polarity of the pwm signal. 0: the pwm signal is not inverted 1: the pwm signal is inverted 0cmpfx pwmx compare flag this bit is set by hardware and cleared by software by reading the pwmxcsr register. it indicates t hat the upcounter value matches the active dcrx register value. 0: upcounter value does not match dcrx value 1: upcounter value matches dcrx value
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 95/236 break control register (breakcr) breakcr reset value: 0000 0000 (00h) 76543210 reserved reserved ba bpen pwm[3:0] - - r/w r/w r/w table 41. breakcr register description bit bit name function 7:6 - reserved, must be kept cleared 5ba break active this bit is read/writen by software, cleared by hardware after reset and set by hardware when the break pin is low. it activates/deactivates the break function. 0: break not active 1: break active 4 bpen break pin enable this bit is read/writen by software and cleared by hardware after reset. 0: break pin disabled 1: break pin enabled 3:0 pwm[3:0] break pattern these bits are read/writen by software and cleared by hardware after a reset. they are used to force the four pwmx output signals into a stable state when the break function is active and corresponding oex bit is set.
on-chip peripherals st7l34, st7l35, st7l38, st7l39 96/236 doc id 11928 rev 7 pwmx duty cycle register high (dcrxh) pwmx duty cycle register low (dcrxl) dcrxh reset value: 0000 0000 (00h) 15 14 13 12 11 10 9 8 reserved reserved reserved reserved dcrx[11:8] ---- r/w dcrxl reset value: 0000 0000 (00h) 7654 3 2 1 0 dcrx[7:0] r/w table 42. dcrxh and dcrx l register descriptions bit bit name function 15:12 - reserved, must be kept cleared 11:0 dcrx[11:0] pwmx duty cycle value this 12-bit value is written by so ftware. it defines the duty cycle of the corresponding pwm output signal (see figure 38: pwm function on page 82 ). in pwm mode (oex = 1 in the pwmcr register) the dcrx[11:0] bits define the duty cycle of the pwmx output signal (see figure 38 ). in output compare mode, they define the value to be compared with the 12-bit upcounter value.
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 97/236 input capture register high (aticrh) input capture register low (aticrl) aticrh reset value: 0000 0000 (00h) 15 14 13 12 11 10 9 8 reserved reserved reserved reserved icr[11:8] ---- r aticrl reset value: 0000 0000 (00h) 7654 3 2 1 0 icr[7:0] r table 43. aticrh and aticrl register descriptions bit bit name function 15:12 - reserved, must be kept cleared 11:0 icr[11:0] input capture data this is a 12-bit register which is readable by software and cleared by hardware after a reset. the aticr register contains the captured value of the 12-bit cntr1 register when a rising or falling edge occurs on the atic or ltic pin (depending on ics). capture will only be performed when the icf flag is cleared.
on-chip peripherals st7l34, st7l35, st7l38, st7l39 98/236 doc id 11928 rev 7 timer control register2 (atcsr2) atcsr2 reset value: 0000 0011 (03h) 7654 3 2 1 0 reserved reserved ics ovfie2 ovf2 encntr2 tran2 tran1 - - r/w r/w r/w r/w r/w r/w table 44. atcsr2 register description bit bit name function 7:6 - reserved, must be kept cleared 5ics input capture shorted this bit is read/writen by software. it allows the attimer cntr1 to use the ltic pin for long input capture. 0: atic for cntr1 input capture 1: ltic for cntr1 input capture 4ovfie2 overflow interrupt 2 enable this bit is read/writen by software and controls the overflow interrupt of counter 2. 0: overflow interrupt disabled 1: overflow interrupt enabled 3ovf2 overflow flag this bit is set by hardware and cleared by software by reading the atcsr2 register. it indicates the transition of the counter 2 from fffh to atr2 value. 0: no counter overflow occurred 1: counter overflow occurred 2 encntr2 enable counter 2 this bit is read/writen by software and switches the second counter cntr2. if this bit is set, pwm2/3 is generated using cntr2 0: cntr2 stopped 1: cntr2 starts running 1 tran2 transfer enable 2 this bit is read/writen by software, cleared by hardware after each completed transfer and set by hardware after reset. it controls the transfers on cntr2. it allows the value of the preload dcrx registers to be transferred to the active dcrx registers after the next overflow event. the opx bits are transferred to the shadow opx bits in the same way. note: only dcr2/3 can be controlled using this bit
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 99/236 autoreload register2 high (atr2h) autoreload register2 low (atr2l) dead time generator register (dtgr) 0 tran1 transfer enable 1 this bit is read/writen by software, cleared by hardware after each completed transfer and set by hardware after reset. it controls the transfers on cntr1. it allows the value of the preload dcrx registers to be transferred to the active dcrx registers after the next overflow event. the opx bits are transferred to the shadow opx bits in the same way. atr2h reset value: 0000 0000 (00h) 15 14 13 12 11 10 9 8 reserved reserved reserved reserved atr2[11:8] ---- r/w atr2l reset value: 0000 0000 (00h) 7654 3 2 1 0 atr2[7:0] r/w table 45. atr2h and atr2l register descriptions bit bit name function 15:12 - reserved, must be kept cleared 11:0 atr2[11:0] autoreload register 2 this is a 12-bit register which is written by software. the atr2 register value is automatically loaded into the upcounter cntr2 when an overflow of cntr2 occurs. the register value is used to set the pwm2/pwm3 frequency when encntr2 is set. dtgr reset value: 0000 0000 (00h) 7654 3 2 1 0 dte dt[6:0] r/w r/w table 44. atcsr2 register description (continued) bit bit name function
on-chip peripherals st7l34, st7l35, st7l38, st7l39 100/236 doc id 11928 rev 7 table 46. dtgr register description bit bit name function 7dte dead time enable this bit is read/writen by software. it enables a dead time generation on pwm0/pwm1. 0: no dead time insertion 1: dead time insertion enabled 6:0 dt[6:0] dead time value these bits are read/writen by software. they define the dead time inserted between pwm0/pwm1. dead time is calculated as follows: dead time = dt[6:0] x tcounter1
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 101/236 table 47. register map and reset values add (hex.) register label 7654 3 2 10 0d at c s r reset value 0 icf 0 icie 0 ck1 0 ck0 0 ovf1 0 ovfie1 0 cmpie 0 0e cntr1h reset value 0000 cntr1_11 0 cntr1_10 0 cntr1_9 0 cntr1_8 0 0f cntr1l reset value cntr1_7 0 cntr1_6 0 cntr1_5 0 cntr1_4 0 cntr1_3 0 cntr1_2 0 cntr1_1 0 cntr1_0 0 10 at r 1 h reset value 0000 at r 1 1 0 at r 1 0 0 at r 9 0 at r 8 0 11 at r 1 l reset value at r 7 0 at r 6 0 at r 5 0 at r 4 0 at r 3 0 at r 2 0 at r 1 0 at r 0 0 12 pwmcr reset value 0 oe3 0 0 oe2 0 0 oe1 0 0 oe0 0 13 pwm0csr reset value 0000 0 0 op0 0 cmpf0 0 14 pwm1csr reset value 0000 0 0 op1 0 cmpf1 0 15 pwm2csr reset value 0000 0 0 op2 0 cmpf2 0 16 pwm3csr reset value 0000 0 0 op3 0 cmpf3 0 17 dcr0h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 18 dcr0l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 19 dcr1h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1a dcr1l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1b dcr2h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1c dcr2l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1d dcr3h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1e dcr3l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1f aticrh reset value 0000 icr11 0 icr10 0 icr9 0 icr8 0 20 aticrl reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0 21 atcsr2 reset value 00 ics 0 ovfie2 0 ovf2 0 encntr2 0 tran2 1 tran1 1
on-chip peripherals st7l34, st7l35, st7l38, st7l39 102/236 doc id 11928 rev 7 11.3 lite timer 2 (lt2) 11.3.1 introduction the lite timer is used for general-purpose timing fu nctions. it is based on two free-running 8-bit upcounters and an 8-bit input capture register. 11.3.2 main features real-time clock (rtc) ? one 8-bit upcounter 1ms or 2ms timebase period (@ 8 mhz f osc ) ) ? one 8-bit upcounter with autoreload and programmable timebase period from 4s to 1.024ms in 4s increments (@ 8 mhz f osc ) ? 2 maskable timebase interrupts input capture ? 8-bit input capture register (lticr) ? maskable interrupt with wakeup from halt mode capability 22 breakcr reset value 00 ba 0 bpen 0 pwm3 0 pwm2 0 pwm1 0 pwm0 0 23 at r 2 h reset value 0000 at r 1 1 0 at r 1 0 0 at r 9 0 at r 8 0 24 at r 2 l reset value at r 7 0 at r 6 0 at r 5 0 at r 4 0 at r 3 0 at r 2 0 at r 1 0 at r 0 0 25 dtgr reset value dte 0 dt6 0 dt5 0 dt4 0 dt3 0 dt2 0 dt1 0 dt0 0 table 47. register map and reset values (continued) add (hex.) register label 7654 3 2 10
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 103/236 figure 47. lite timer 2 block diagram ltcsr1 8-bit timebase counter 1 /2 8-bit f lti m e r 8 lt i c f osc/32 tb1f tb1ie tb icf icie lttb1 interrupt request ltic interrupt request lt i c r input capture register 1 0 1 or 2 ms timebase (@ 8 mhz f osc ) to 12-bit at timer f lti m e r ltcsr2 tb2f 0 tb2ie 0 lttb2 8-bit timebase counter 2 0 0 8-bit autoreload register 8 lt c n t r lta r r 0 0 interrupt request
on-chip peripherals st7l34, st7l35, st7l38, st7l39 104/236 doc id 11928 rev 7 11.3.3 functional description timebase counter 1 the 8-bit value of counter 1 cannot be read or written by software. after an mcu reset, it starts incrementing from 0 at a frequency of f osc /32. an overflow event occurs when the counter rolls over from f9h to 00h. if f osc = 8 mhz, then the time period between two counter overflow events is 1 ms. this period can be doubled by setting the tb bit in the ltcsr1 register. when counter 1 overflows, the tb1f bit is set by hardware and an interrupt request is generated if the tb1ie bit is set. the tb1f bit is cleared by software reading the ltcsr1 register. timebase counter 2 counter 2 is an 8-bit autoreload upcounter. it can be read by accessing the ltcntr register. after an mcu reset, it increments at a frequency of f osc /32 starting from the value stored in the ltarr register. a counter overflow event occurs when the counter rolls over from ffh to the ltarr reload value. software can write a new value at anytime in the ltarr register, this value will be automatically loaded in the co unter when the next overflow occurs. when counter 2 overflows, the tb2f bit in the ltcsr2 register is set by hardware and an interrupt request is generated if the tb2ie bit is set. the tb2f bit is cleared by software reading the ltcsr2 register. input capture the 8-bit input capture register is used to latch the free-running upcounter (counter 1) 1 after a rising or falling edge is detected on the ltic pin. when an input capture occurs, the icf bit is set and the lticr register contains the value of counter 1. an interrupt is generated if the icie bit is set. the icf bit is cleared by reading the lticr register. the lticr is a read-only register and always contains the data from the last input capture. input capture is inhibited if the icf bit is set. figure 48. input capture timing diagram 04h 8-bit counter 1 t 01h f osc/32 xxh 02h 03h 05h 06h 07h 04h lt i c p i n icf flag lt i c r r e g i s t e r cleared 4s (@ 8 mhz f osc ) f cpu by s/w 07h reading ltic register
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 105/236 11.3.4 low power modes table 48. effect of low power modes on lite timer 2 mode description slow no effect on lite timer (this peripheral is driven directly by f osc /32) wait no effect on lite timer active halt halt lite timer stops counting table 49. lite timer 2 interrupt control/wake-up capability (1) 1. the tbxf and icf interrupt events are connec ted to separate interrupt vectors (see section 8: interrupts ). they generate an interrupt if the enable bit is set in the ltcsr1 or ltcsr2 register and the interrupt mask in the cc register is re set (rim instruction). interrupt event event flag enab le control bit exit from wait exit from active halt exit from halt timebase 1 event tb1f tb1ie ye s ye s no timebase 2 event tb2f tb2ie no ic event icf icie
on-chip peripherals st7l34, st7l35, st7l38, st7l39 106/236 doc id 11928 rev 7 11.3.5 register description lite timer control/status register 2 (ltcsr2) lite timer autoreload register (ltarr) ltcsr2 reset value: 0x00 0000 (x0h) 7654 3 2 1 0 reserved reserved reserved reserv ed reserved reserved tb2ie tb2f ---- - -r/wr/w table 50. ltcsr2 register description bit bit name function 7:2 - reserved, must be kept cleared 1tb2ie timebase 2 interrupt enable this bit is set and cleared by software. 0: timebase (tb2) interrupt disabled 1: timebase (tb2) interrupt enabled 0tb2f timebase 2 interrupt flag this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter 2 overflow 1: a counter 2 overflow has occurred ltarr reset value: 0000 0000 (00h) 7654 3 2 1 0 ar[7:0] r/w table 51. ltarr register description bit bit name function 7:0 ar[7:0] counter 2 reload value these bits are read/writen by software. the ltarr value is automatically loaded into counter 2 (ltcntr) when an overflow occurs.
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 107/236 lite timer counter 2 (ltcntr) lite timer control/status register (ltcsr1) ltcntr reset value: 0000 0000 (00h) 7654 3 2 1 0 cnt[7:0] r table 52. ltcntr register description bit bit name function 7:0 cnt[7:0] counter 2 reload value this register is read by software. the ltarr value is automatically loaded into counter 2 (ltcntr) when an overflow occurs. ltcsr1 reset value: 0x00 0000 (x0h) 7654 3 2 1 0 icie icf tb tb1ie tb1f reserved reserved reserved r/w r/w r/w r/w r/w - - - table 53. ltcsr1 register description bit bit name function 7icie interrupt enable this bit is set and cleared by software. 0: input capture (ic) interrupt disabled 1: input capture (ic) interrupt enabled 6icf input capture flag this bit is set by hardware and cleared by software by reading the lticr register. writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred note: after an mcu reset, software must initialize the icf bit by reading the lticr register 5tb timebase period selection this bit is set and cleared by software. 0: timebase period = t osc * 8000 (1ms @ 8 mhz) 1: timebase period = t osc * 16000 (2ms @ 8 mhz) 4tb1ie timebase interrupt enable this bit is set and cleared by software. 0: timebase (tb1) interrupt disabled 1: timebase (tb1) interrupt enabled
on-chip peripherals st7l34, st7l35, st7l38, st7l39 108/236 doc id 11928 rev 7 lite timer input capture register (lticr) 3tb1f timebase interrupt flag this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter overflow 1: a counter overflow has occurred 2:0 - reserved, must be kept cleared lticr reset value: 0000 0000 (00h) 7654 3 2 1 0 icr[7:0] r table 54. lticr register description bit bit name function 7:0 icr[7:0] input capture value these bits are read by software and cleared by hardware after a reset. if the icf bit in the ltcsr is cleared, the value of the 8-bit up- counter is captured when a rising or falling edge occurs on the ltic pin. table 55. lite timer register map and reset values address (hex.) register label 765432 10 08 ltcsr2 reset value 0 0 0 0 0 0 tb2ie 0 tb2f 0 09 lta r r reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0 0a ltcntr reset value cnt7 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 0b ltcsr1 reset value icie 0 icf x tb 0 tb1ie 0 tb1f 0 000 0c lt i c r reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0 table 53. ltcsr1 register description (continued) bit bit name function
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 109/236 11.4 serial peripheral interface (spi) 11.4.1 introduction the serial peripheral interface (spi) allows full-duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 11.4.2 main features full duplex synchronous transfers (on three lines) simplex synchronous transfers (on two lines) master or slave operation 6 master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note below) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag write collision, master mo de fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 11.4.3 general description figure 49: serial peripheral interface block diagram on page 110 shows the serial peripheral interface (spi) block diagram. there are three registers: ? spi control register (spicr) ? spi control/status register (spicsr) ? spi data register (spidr) the spi is connected to external devices through four pins: ? miso: master in/slave out data ? mosi:master out/slave in data ? sck: serial clock out by spi masters and input by spi slaves ?ss : slave select:this input signal acts as a ?chip select? to let the spi master communicate with slaves individually and to avoid contention on the data lines. slave ss inputs can be driven by standard i/o ports on the master device.
on-chip peripherals st7l34, st7l35, st7l38, st7l39 110/236 doc id 11928 rev 7 figure 49. serial peripheral interface block diagram functional description a basic example of interconnectio ns between a single ma ster and a single slave is illustrated in figure 50: single master/single slave application on page 111 . the mosi pins are connected together and the miso pins are connected together. in this way data are transferred serially between master and slave (most significant bit first). the communication is always initiated by the master. when the master device transmits data to a slave device via mosi pin, the slave device responds by se nding data to the master device via the miso pin. this implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node (in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 53: data clock timing diagram on page 115 ) but master and slave must be programmed with the same timing mode. spidr read buffer 8-bit shift register write read data/address bus spi state control spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 111/236 figure 50. single master/s ingle slave application slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr register (see figure 52: hardware/software slave select management on page 112 ). in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ?ss internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 51: generic ss timing diagram on page 112 ): if cpha = 1 (data latched on second clock edge): ?ss internal must be held low during the entire transmission. this implies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by managing the ss function by software (ssm = 1 and ssi = 0 in the in the spicsr register) if cpha = 0 (data latched on first clock edge): ?ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. if ss is not pulled high, a write collision error occurs when the slav e writes to the sh ift register (see write collision error (wcol) on page 116 ). 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5 v msbit lsbit msbit lsbit not used if ss is managed by software
on-chip peripherals st7l34, st7l35, st7l38, st7l39 112/236 doc id 11928 rev 7 figure 51. generic ss timing diagram figure 52. hardware/software slave select management master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). how to operate the spi in master mode to operate the spi in master mode, perform the following steps in order: 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits. ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 53: data clock timing diagram on page 115 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits note: 1 mstr and spe bits remain set only if ss is high). 2 if the spicsr register is not written first, the spicr register setting (mstr bit) may be not taken into account. the transmit sequence begins when software writes a byte in the spidr register. byte 1 byte 2 byte 3 mosi/miso master ss slave ss (if cpha = 0) slave ss (if cpha = 1) 1 0 ss internal ssm bit ssi bit ss external pin
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 113/236 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the following actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 53: data clock timing diagram on page 115 ). note: the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in slave select management on page 111 and figure 51: generic ss timing diagram on page 112 . if cpha = 1 ss must be held low continuously. if cpha = 0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and se t the spe bit to enable the spi i/o functions. slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its mosi pin. when data transfer is complete: ? the spif bit is set by hardware. ? an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a write or a read to the spidr register
on-chip peripherals st7l34, st7l35, st7l38, st7l39 114/236 doc id 11928 rev 7 note: 1 while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. 2 the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see overrun condition (ovr) on page 116 ). 11.4.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 53: data clock timing diagram on page 115 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge. figure 53: data clock timing diagram on page 115 shows an spi transfer with the four combinations of the cpha and cpol bits. the diagram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin and the mosi pin are directly connected between the master and the slave device. note: if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit.
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 115/236 figure 53. data clock timing diagram 1. this figure should not be used as a replac ement for parametric information. refer to section 13: electrical characteristics . msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) ss (to slave) capture strobe cpha = 0 cpha = 1 (cpol = 1) sck (cpol = 0) sck mosi (from slave) msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) ss (to slave) capture strobe (cpol = 1) sck (cpol = 0) sck mosi (from slave)
on-chip peripherals st7l34, st7l35, st7l38, st7l39 116/236 doc id 11928 rev 7 11.4.5 error flags master mode fault (modf) master mode fault occurs when the master device?s ss pin is pulled low. when a master mode fault occurs: ? the modf bit is set and an spi interrupt request is generated if the spie bit is set. ? the spe bit is reset. this blocks all out put from the device and disables the spi peripheral. ? the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read access to the spicsr regi ster while the modf bit is set. 2. a write to the spicr register. note: 1 to avoid any conflicts in an ap plication with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their original state during or after this clearing sequence. 2 hardware does not allow the us er to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. 3 in a slave device, the modf bit can not be set, but in a multimaster configuration the device can be in slave mode with the modf bit set. 4 the modf bit indicates that there might have been a multimaster conflict and allows software to handle this using an interrupt routine and either perform a reset or return to an application default state. overrun condition (ovr) an overrun condition occurs when the master device has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. write collision error (wcol) a write collision occurs when the software trie s to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted and the softwa re write will be unsuccessful. write collisions can occur both in master and slave mode. see also slave select management on page 111 . note: a ?read collision? w ill never occur since the received data byte is placed in a buffer in which access is always synchronous with the cpu operation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only).
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 117/236 clearing the wcol bit is done through a software sequence (see figure 54 ). figure 54. clearing the wcol bit (write collision flag) software sequence 1. writing to the spidr register instead of reading it does not reset the wcol bit. single master and multimaster configurations there are two types of spi systems: single master system multimaster system single master system a typical single master system may be configured using a device as the master and four devices as slaves (see figure 55: single master/multiple slave configuration on page 118 ). the master device selects the individual slave devices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line, the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are connected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with command fields. multimaster system a multimaster system may also be configured by the user. transfer of master control could be implemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multimaster system is principally handled by the mstr bit in the spicr register and the modf bit in the spicsr register. clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif = 0 wcol = 0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol = 0 read spicsr read spidr result result
on-chip peripherals st7l34, st7l35, st7l38, st7l39 118/236 doc id 11928 rev 7 figure 55. single master/mul tiple slave configuration 11.4.6 low power modes using the spi to wake up the device from halt mode in slave configuration, the spi is able to wake up the device from halt mode through a spif interrupt. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetch). if multiple data transfers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to perform an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake up the device from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the device enters halt mode. so, if slave selection is configured as external (see slave select management on page 111 ), make sure the master drives a low level on the ss pin when the slave enters halt mode. miso mosi ss sck 5 v por ts master ss sck mosi miso slave device ss sck mosi miso slave device ss sck mosi miso slave device ss sck mosi miso slave device device table 56. effect of low power modes on spi mode description wait no effect on spi spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen in halt mode, the spi is inactive. spi operation resumes when the device is woken up by an interrupt with ?exit from halt mode? capability. the data received is subsequently read from the spidr r egister when the software is running (interrupt vector fetching). if several data are received before the wakeup event, then an overrun error is generated. this error can be detected after the fetch of the interrupt routine that woke up the device.
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 119/236 11.4.7 interrupts 11.4.8 register description spi control register (spicr) table 57. spi interrupt control/wake-up capability (1) 1. the spi interrupt events are connecte d to the same interrupt vector (see section 8: interrupts ). they generate an interrupt if the corresponding enable control bi t is set and the interrupt mask in the cc register is reset (rim instruction). interrupt event event flag enable cont rol bit exit from wait exit from halt spi end of transfer event spif spie yes ye s master mode fault event modf no overrun error ovr spicr reset value: 0000 xxxx (0xh) 76543210 spie spe spr2 mstr cpol cpha spr[1:0] r/w r/w r/w r/w r/w r/w r/w table 58. spicr register description bit bit name function 7 spie s erial peripheral interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever an end of transfer event, master mode fault or overrun error occurs ( spif = 1, modf = 1 or ovr = 1 in the spicsr register) 6 spe serial peripheral output enable this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see master mode fault (modf) on page 116 ). the spe bit is cleared by re set, so the spi peripheral is not initially connected to the external pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled 5 spr2 divider enable this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate (see bits [1:0] below). 0: divider by 2 enabled 1: divider by 2 disabled note: the spr2 bit has no effect in slave mode
on-chip peripherals st7l34, st7l35, st7l38, st7l39 120/236 doc id 11928 rev 7 4mstr master mode this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see master mode fault (modf) on page 116 ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are reversed. 3cpol clock polarity this bit is set and cleared by software. this bit determines the idle state of the serial clock. the cp ol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note: if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit. 2cpha clock phase this bit is set and cleared by software. 0: the first clock transition is the first data capture edge 1: the second clock transition is the first capture edge note: the slave must have the same cpol and cpha settings as the master. 1:0 spr[1:0] serial clock frequency these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode: 100: serial clock = f cpu /4 000: serial clock = f cpu /8 001: serial clock = f cpu /16 110: serial clock = f cpu /32 010: serial clock = f cpu /64 011: serial clock = f cpu /128 note: these 2 bits have no effect in slave mode. table 58. spicr register description (continued) bit bit name function
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 121/236 spi control/status register (spicsr) spicsr reset value: 0000 0000 (00h) 76543210 spif wcol ovr modf reserved sod ssm ssi r r r r - r/w r/w r/w table 59. spicsr register description bit bit name function 7 spif serial peripheral data transfer flag this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie = 1 in the spicr register. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared 1: data transfer between the device and an external device has been completed note: while the spif bit is set, a ll writes to the spidr register are inhibited until the spicsr register is read. 6wcol write collision status this bit is set by hardware when a write to the spidr register is made during a transmit sequence. it is cleared by a software sequence (see figure 54: clearing the wcol bit (write collision flag) software sequence on page 117 ). 0: no write collision occurred 1: a write collision has been detected 5ovr spi overrun error this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see overrun condition (ovr) on page 116 ). an interrupt is generated if spie = 1 in spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected 4modf mode fault flag this bit is set by hardware when the ss pin is pulled low in master mode (see master mode fault (modf) on page 116 ). an spi interrupt can be generated if spie = 1 in the spicr register. this bit is cleared by a software sequence (an access to the spicsr register while modf = 1 followed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected 3 - reserved, must be kept cleared.
on-chip peripherals st7l34, st7l35, st7l38, st7l39 122/236 doc id 11928 rev 7 spi data i/o register (spidr) the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this register initiates transmission/reception of another byte. note: 1 during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. 2 while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value located in the buffer and not the content of the shift register (see figure 49: serial peripheral interface block diagram on page 110 ). 2sod spi output disable this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode/miso in slave mode). 0: spi output enabled (if spe = 1) 1: spi output disabled 1 ssm ss management this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see slave select management on page 111 . 0: hardware management (ss managed by external pin) 1: software management (internal ss signal controlled by ssi bit. external ss pin free for general-purpose i/o) 0 ssi ss internal mode this bit is set and cleared by software. it acts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0 : slave selected 1 : slave deselected spidr reset value: undefined 76543210 d[7:0] r/w table 59. spicsr register description (continued) bit bit name function
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 123/236 11.5 linsci serial communicat ion interface (lin master/slave) 11.5.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci offers a very wide range of baud rates using two baud rate generator systems. the lin-dedicated features support the lin (loc al interconnect network) protocol for both master and slave nodes. this chapter is divided into sci mode and lin mode sections. for information on general sci communications, refer to the sci mode section. for lin applications, refer to both the sci mode and lin mode sections. table 60. spi register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 0031h spidr reset value msb xxxxxxx lsb x 0032h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0033h spicsr reset value spif 0 wcol 0 ovr 0 modf 00 sod 0 ssm 0 ssi 0
on-chip peripherals st7l34, st7l35, st7l38, st7l39 124/236 doc id 11928 rev 7 11.5.2 sci features full duplex, asynchronous communications nrz standard format (mark/space) independently programmable transmit and receive baud rates up to 500 k baud programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags 2 receiver wake-up modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver overrun, noise and frame error detection 6 interrupt sources ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error ? parity interrupt parity control: ? transmits parity bit ? checks parity of received data byte reduced power consumption mode 11.5.3 lin features lin master ? 13-bit lin synch break generation lin slave ? automatic header handling ? automatic baud rate resynchronization based on recognition and measurement of the lin synch field (for lin slave nodes) ? automatic baud rate adjustment (at cpu frequency precision) ? 11-bit lin synch break detection capability ? lin parity check on the lin identifier field (only in reception) ? lin error management ? lin header timeout ? hot plugging support
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 125/236 11.5.4 general description the interface is externally connected to another device by two pins: tdo: transmit data output. when the transmitter is disabled, the output pin returns to its i/o port configuration. when the transmitter is enabled and nothing is to be transmitted, the tdo pin is at high level. rdi: receive data input is the serial data input. oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as characters comprising: an idle line prior to tr ansmission or reception a start bit a data word (8 or 9 bits) least significant bit first a stop bit indicating that the character is complete this interface uses three types of baud rate generator: a conventional type for commonly-used baud rates an extended type with a prescaler offering a very wide range of baud rates even with non-standard osc illator frequencies a lin baud rate generator with automatic resynchronization
on-chip peripherals st7l34, st7l35, st7l38, st7l39 126/236 doc id 11928 rev 7 figure 56. sci block diagram (in conventional baud rate generator mode) 11.5.5 sci mode - functional description conventional baud rate generator mode the block diagram of the serial control interface in conventional baud rate generator mode is shown in figure 56 . it uses four registers: 2 control registers (scicr1 and scicr2) a status register (scisr) a baud rate register (scibrr) extended prescaler mode wake up unit receiver control scisr transmit control tc nf fe pe sci interrupt control scicr1 r8 t8 m wa pce ps pie received data register (rdr) receive shift register read transmit data register (tdr) transmit shift register write rdi tdo ( data register) scidr transmitter clock receiver clock transmitter rate scibrr f cpu control /pr /16 conventional baud rate generator sbk re te ilie rie tie scicr2 ke sc id or lhe id le td re rd rf rw u tc ie sc p1 sc t2 sc r1 receiver rate control sc p0 sc t0 sc t1 sc r2 sc r0
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 127/236 two additional prescalers are available in extended prescaler mode. they are shown in figure 58: sci baud rate and extended prescaler block diagram on page 132 . an extended prescaler receiver register (scierpr) an extended prescaler transmitter register (scietpr) serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 register (see figure 57 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as a continuou s logic high level for 10 (or 11) full bit times. a break character is a character with a sufficient number of low level bits to break the normal data format followed by an extra ?1? bit to acknowledge the start bit. figure 57. word length programming transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. character transmission bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle line bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle line start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit break character start bit extra ?1? data character break character extra ?1? data character next data character next data character possible parity bit start bit
on-chip peripherals st7l34, st7l35, st7l38, st7l39 128/236 doc id 11928 rev 7 during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 56 ). procedure select the m bit to define the word length. select the desired baud rate using the scibrr and the scietpr registers. set the te bit to send a preamble of 10 (m = 0) or 11 (m = 1) consecutive ones (idle line) as first transmission. access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: the tdr register is empty the data transfer is beginning the next data can be written in the scidr register without overwriting the previous data this flag generates an interrupt if the tie bit is set and the i[|1:0] bits are cleared in the ccr register. when a transmission is taking place, a write instruction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write instruction to the scidr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a character transmission is complete (aft er the stop bit) the tc bit is set and an interrupt is generated if the tcie is set and the i[1:0] bits are cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the sh ift register with a break character. th e break character length depends on the m bit (see figure 57: word length programming on page 127 ). as long as the sbk bit is set, the sci sends br eak characters to the tdo pin. after clearing this bit by software, the sci inserts a logic 1 bit at the end of the last break character to guarantee the recognition of the start bit of the next character. idle line setting the te bit drives the sci to send a preamble of 10 (m = 0) or 11 (m = 1) consecutive ?1?s (idle line) before the first character.
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 129/236 in this case, clearing and then setting the te bit during a transmission sends a preamble (idle line) after the current word. note that the preamble duration (10 or 11 consecutive ?1?s depending on the m bit) does not take into account the stop bit of the previous character. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set, that is, before writing the next byte in the scidr. receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least significant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) between the internal bus and the received shift register (see figure 56: sci block diagram (in conventional baud rate generator mode) on page 126 ). procedure select the m bit to define the word length. select the desired baud rate using the scibrr and the scierpr registers. set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr an interrupt is generated if the rie bit is set and the i[1:0] bits are cleared in the ccr register the error flags can be set if a frame error, noise or an overrun error has been detected during reception clearing the rdrf bit is performed by th e following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. idle line when an idle line is detected, there is the same procedure as a data received character plus an interrupt if the ilie bit is set and the i[|1:0] bits ar e cleared in the ccr register. overrun error an overrun error occurs when a character is received when rdrf has not been reset. data can not be transferred from the shift register to the tdr register as long as the rdrf bit is not cleared.
on-chip peripherals st7l34, st7l35, st7l38, st7l39 130/236 doc id 11928 rev 7 when an overrun error occurs: the or bit is set the rdr content will not be lost the shift register will be overwritten an interrupt is generated if the rie bit is set and the i[|1:0] bits are cleared in the ccr register. the or bit is reset by an access to the scisr register followed by a scidr register read operation. noise error oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. when noise is detected in a character: the nf bit is set at the rising edge of the rdrf bit data is transferred from the shift register to the scidr register no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt the nf bit is reset by a scisr register read operation followed by a scidr register read operation. framing error a framing error is detected when: the stop bit is not recognized on reception at the expected time, following either a desynchronization or excessive noise. a break is received when the framing error is detected: the fe bit is set by hardware data is transferred from the shift register to the scidr register no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read operation followed by a scidr register read operation. break character when a break character is received, the sci handles it as a framing error. to differentiate a break character from a framing error, it is necessary to read the scidr. if the received value is 00h, it is a break character. otherwise it is a framing error. conventional baud rate generation the baud rates for the receiver and transmitter (rx and tx) are set independently and calculated as follows: where: tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 131/236 pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all these bits are in the baud rate register (scibrr) on page 140 . example: if f cpu is 8 mhz (normal mode) and if pr = 13 and tr = rr = 1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is enabled. extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional baud rate generator retains industry standard software compatibility. the extended baud rate generator block diagram is described in figure 58: sci baud rate and extended prescaler block diagram on page 132 . the output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the scierpr or the scietpr register. note: the extended prescaler is activated by setting the scietpr or scierpr register to a value other than zero. the baud rates are calculated as follows: where: etpr = 1, ..., 255 (see scietpr register on page 142 ) erpr = 1, ..., 255 (see scierpr register on page 142 ) tx = 16 * etpr*(pr*tr) f cpu rx = 16 * erpr*(pr*rr) f cpu
on-chip peripherals st7l34, st7l35, st7l38, st7l39 132/236 doc id 11928 rev 7 figure 58. sci baud rate and extended prescaler block diagram receiver muting and wake-up feature in multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non-addressed receivers. the non-addressed devices may be placed in sleep mode by means of the muting function. transmitter clock receiver clock scietpr scierpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler receiver rate control transmitter rate control scibrr scp1 f cpu scp0 sct2 sct1 sct0 scr2 scr1 scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 133/236 setting the rwu bit by software puts the sci in sleep mode: all the reception status bits cannot be set. all the receive interrupts are inhibited. a muted receiver may be woken up in one of the following ways: by idle line detection if the wake bit is reset, by address mark detection if the wake bit is set. idle line detection the receiver wakes up by idle line detection when the receiv e line has recogn ized an idle line. then the rwu bit is reset by hardware but the idle bit is not set. this feature is useful in a multiprocessor system when the first characters of the message determine the address and when each message ends by an idle line: as soon as the line becomes idle, every receivers is waken up and analyse the first characters of the message which indicates the addressed receiver. the receivers which are not addressed set rwu bit to enter in mute mode. consequ ently, they will not treat the ne xt characters constituting the next part of the message. at the end of the message, an idle line is sent by the transmitter: this wakes up every receivers which are ready to analyse the addressing characters of the new message. in such a system, the inter-characters space must be smaller than the idle time. address mark detection the receiver wakes up by address mark detection when it receives a ?1? as the most significant bit of a word, thus indicating that the message is an address. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. this feature is useful in a multiprocessor s ystem when the most significant bit of each character (except for the break character) is reserved for address detection. as soon as the receivers receive an address character (most significant bit = ?1?), the receivers are woken up. the receivers which are not addressed set rwu bit to enter in mute mode. consequently, they will not treat the next characters constitu ting the next part of the message. parity control hardware byte parity control (generation of pari ty bit in transmission and parity checking in reception) can be enabled by setting the pce bit in the scicr1 register. depending on the character format defined by the m bit, the possible sci character formats are as listed in ta bl e 6 1 . note: in case of wake-up by an address mark, the msb bit of the data is taken into account and not the parity bit table 61. character formats (1) m bit pce bit character format 0 0 | sb | 8 bit data | stb | 1 | sb | 7-bit data | pb | stb |
on-chip peripherals st7l34, st7l35, st7l38, st7l39 134/236 doc id 11928 rev 7 even parity the parity bit is calculated to obtain an even number of ?1s? inside the character made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. example: data = 001101 01; 4 bits set => parity bit will be 0 if even parity is selected (ps bit = 0). odd parity the parity bit is calculated to obtain an odd nu mber of ?1s? inside the character made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. example: data = 001101 01; 4 bits set => parity bit will be 1 if odd parity is selected (ps bit = 1). transmission mode if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode if the pce bit is set then the interface checks if the received data byte has an even number of ?1s? if even parity is selected (ps = 0) or an odd number of ?1s? if odd parity is selected (ps = 1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is generated if pcie is set in the scicr1 register. 11.5.6 low power modes 1 0 | sb | 9-bit data | stb | 1 | sb | 8-bit data | pb | stb | 1. legend: sb = start bit, stb = stop bit, pb = parity bit table 61. character formats (1) table 62. effect of low power modes on sci mode description wait no effect on sci sci interrupts cause the device to exit from wait mode halt sci registers are frozen in halt mode, the sci stops transmitting/receiving until halt mode is exited
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 135/236 11.5.7 interrupts the sci interrupt events are connected to the same interrupt vector (see section 8: interrupts ). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 11.5.8 sci mode registers status register (scisr) table 63. sci interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie ye s n o transmission complete tc tcie received data ready to be read rdrf rie overrun error or lin synch error detected or/lhe idle line detected idle ilie parity error pe pie lin header detection lhdf lhie scisr reset value: 1100 0000 (c0h) 76543210 tdre tc rdrf idle or (1) 1. this bit has a different function in lin mode, please refer to the lin mode register description nf (1) fe (1) pe (1) rrrrrrrr
on-chip peripherals st7l34, st7l35, st7l38, st7l39 136/236 doc id 11928 rev 7 table 64. scisr register description bit bit name function 7tdre transmit data register empty this bit is set by hardware when th e content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie bit = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register 6tc transmission complete this bit is set by hardware when transmission of a character containing data is complete. an interrupt is generated if tcie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a preamble or a break. 5 rdrf received data ready flag this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interrupt is generated if rie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: data are not received 1: received data are ready to be read 4idle idle line detect this bit is set by hardware when an idle line is detected. an interrupt is generated if the ilie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit is not set again until the rdrf bit is set (i.e. a new idle line occurs). 3or overrun error this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf = 1. an interrupt is generated if rie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no overrun error 1: overrun error is detected note: when the idle bit is set the rdr register content is not lost but the shift register is overwritten.
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 137/236 control register 1 (scicr1) 2nf noise flag this bit is set by hardware when noise is detected on a received character. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no noise is detected 1: noise is detected note: the nf bit does not generate an interrupt as it appears at the same time as the rdrf bit which itself generates an interrupt. 1fe framing error this bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error is detected 1: framing error or break character is detected note: the fe bit does not generate an interrupt as it appears at the same time as the rdrf bit which itself generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it is transferred and only the or bit is set. 0pe parity error this bit is set by hardware when a parity error occurs (if the pce bit is set) in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an interrupt is generated if pie = 1 in the scicr1 register. 0: no parity error 1: parity error scicr1 reset value: x000 0000 (x0h) 76543210 r8 t8 scid m wake pce (1) 1. this bit has a different function in lin mode, please refer to the lin mode register description ps pie r/w r/w r/w r/w r/w r/w r/w r/w table 65. scicr1 register description bit bit name function 7r8 receive data bit 8 this bit is used to store the 9th bit of the received word when m = 1. 6t8 transmit data bit 8 this bit is used to store the 9th bit of the transmitted word when m=1. table 64. scisr register description (continued) bit bit name function
on-chip peripherals st7l34, st7l35, st7l38, st7l39 138/236 doc id 11928 rev 7 control register 2 (scicr2) 5scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped at the end of the current byte transfer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled 4m word length this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note: the m bit must not be modified during a data transfer (both transmission and reception). 3 wake wake up method this bit determines the sci wake up method, it is set or cleared by software. 0: idle line 1: address mark note: if the line bit is set, the wa ke bit is deactivated and replaced by the lhdm bit. 2pce parity control enable this bit is set and cleared by software. it selects the hardware parity control (generation and detection for byte parity, detection only for lin parity). 0: parity control disabled 1: parity control enabled 1ps parity selection this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity is selected after the current byte. 0: even parity 1: odd parity 0pie parity interrupt enable this bit enables the interrupt capabi lity of the hardware parity control when a parity error is detected (pe bit set). the parity error involved can be a byte parity error (if bit pce is set and bit lpe is reset) or a lin parity error (if bit pce is set and bit lpe is set). 0: parity error interrupt disabled 1: parity error interrupt enabled scicr2 reset value: 0000 0000 (00h) 76543210 tie tcie rie ilie te re rwu (1) sbk (1) r/w r/w r/w r/w r/w r/w r/w r/w table 65. scicr1 register description (continued) bit bit name function
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 139/236 1. this bit has a different function in lin mode, please refer to the lin mode register description table 66. scicr2 register description bit bit name function 7tie transmitter interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre = 1 in the scisr register 6tcie transmission complete interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc = 1 in the scisr register 5rie receiver interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or = 1 or rdrf = 1 in the scisr register 4ilie idle line interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle = 1 in the scisr register 3te transmitter enable this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled note: during transmission, an ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. when te is set there is a 1 bit-time delay before the transmission starts. 2re receiver enable this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled in the scisr register 1: receiver is enabled and begins searching for a start bit
on-chip peripherals st7l34, st7l35, st7l38, st7l39 140/236 doc id 11928 rev 7 data register (scidr) contains the received or transmitted data character, depending on whether it is read from or written to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (t dr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift register (see figure 56: sci block diagram (in conventional baud rate generator mode) on page 126 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 56 ). baud rate register (scibrr) 1rwu receiver wake up this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: before selecting mute mode (by setting the rwu bit), the sci must first receive a data byte, otherwise it cannot function in mute mode with wakeup by idle line detection. in address mark detection wake up configuration (wake bit = 1) the rwu bit cannot be modified by software while the rdrf bit is set. 0 sbk send break this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1? and then to ?0?, the transmitter sends a break word at the end of the current word. scidr reset value: undefined 76543210 dr[7:0] r/w scibrr reset value: 0000 0000 (00h) 76543210 table 66. scicr2 register description (continued) bit bit name function
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 141/236 note: when lin slave mode is disabled, the scibrr register controls the conventional baud rate generator. scp[1:0] sct[2:0] scr[2:0] r/w r/w r/w table 67. scibrr register description bit bit name function 7:6 scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: 00: pr prescaling factor = 1 01: pr prescaling factor = 3 10: pr prescaling factor = 4 11: pr prescaling factor = 13 5:3 sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with t he scp1 and scp0 bits define the total division applied to the bus cloc k to yield the transmit rate clock in conventional baud rate generator mode: 000: tr dividing factor = 1 001: tr dividing factor = 2 010: tr dividing factor = 4 011: tr dividing factor = 8 100: tr dividing factor = 16 101: tr dividing factor = 32 110: tr dividing factor = 64 111: tr dividing factor = 128 2:0 scr[2:0] sci receiver rate divider these 3 bits, in conjunction with the scp[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode: 000: rr dividing factor = 1 001: rr dividing factor = 2 010: rr dividing factor = 4 011: rr dividing factor = 8 100: rr dividing factor = 16 101: rr dividing factor = 32 110: rr dividing factor = 64 111: rr dividing factor = 128
on-chip peripherals st7l34, st7l35, st7l38, st7l39 142/236 doc id 11928 rev 7 extended receive prescaler division register (scierpr) extended transmit prescaler division register (scietpr) 11.5.9 lin mode - functional description. the block diagram of the serial control interface, in lin slave mode is shown in figure 60: sci block diagram in lin slave mode on page 145 . scierpr reset value: 0000 0000 (00h) 76543210 erpr[7:0] r/w table 68. scierpr register description bit bit name function 7:0 erpr[7:0] 8-bit extended receive prescaler register the extended baud rate generator is activated when a value different from 00h is stored in this regi ster. therefore the clock frequency issued from the 16 divider (see figure 58: sci baud rate and extended prescaler block diagram on page 132 ) is divided by the binary factor set in the scierp r register (in the range 1 to 255). the extended baud rate generator is not active after a reset. scietpr reset value: 0000 0000 (00h) 76543210 etpr[7:0] r/w table 69. scietpr register description bit bit name function 7:0 etpr[7:0] 8-bit extended transmit prescaler register the extended baud rate generator is activated when a value different from 00h is stored in this regi ster. therefore the clock frequency issued from the 16 divider (see figure 58: sci baud rate and extended prescaler block diagram on page 132 ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not used after a reset. note: in lin slave mode, the conventional and extended baud rate generators are disabled.
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 143/236 it uses six registers: 3 control registers: scicr1, scicr2 and scicr3 2 status registers: scisr register and lhlr register mapped at the scierpr address a baud rate register: lpr mapped at the scibrr address and an associated fraction register lpfr mapped at the scietpr address the bits dedicated to lin are located in the scicr3. refer to the register descriptions in section 11.5.10: lin mode register description for the definitions of each bit. entering lin mode to use the linsci in lin mode the following configuration must be set in scicr3 register: clear the m bit to configure 8-bit word length. set the line bit. master to enter master mode the lslv bit must be reset in this case, setting the sbk bit will send 13 low bits. then the baud rate can programmed using the scibrr, scierpr and scietpr registers. in lin master mode, the conventional and/or extended prescaler define the baud rate (as in standard sci mode) slave set the lslv bit in the scicr3 register to enter lin slave mode. in this case, setting the sbk bit will have no effect. in lin slave mode the lin baud rate generator is selected instead of the conventional or extended prescaler. the lin baud rate generator is common to the transmitter and the receiver. then the baud rate can be programmed using lpr and lprf registers. note: it is mandatory to set the lin configuration first before programming lpr and lprf, because the lin configuration uses a different baud rate generator from the standard one. lin transmission in lin mode the same procedure as in sci mode has to be applied for a lin transmission. to transmit the lin header the proceed as follows: first set the sbk bit in the scicr2 register to start transmitting a 13-bit lin synch break reset the sbk bit load the lin synch field (0x55) in the scidr register to request synch field transmission wait until the scidr is empty (tdre bit set in the scisr register) load the lin message identifier in the scidr register to request identifier transmission.
on-chip peripherals st7l34, st7l35, st7l38, st7l39 144/236 doc id 11928 rev 7 figure 59. lin characters bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit idle line 8-bit word length (m bit is reset) lin synch break = 13 low bits extra ?1? data character next data character lin synch field lin synch field measurement for baud rate autosynchronization start bit start bit next start bit stop bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 start bit
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 145/236 figure 60. sci block diagram in lin slave mode lin reception in lin mode the reception of a byte is the same as in sci mode but the linsci has features for handling the lin header automatically (identifier detection) or semi-automatically (synch break detection) depending on the lin header detection mode. the detection mode is selected by the lhdm bit in the scicr3. wake unit receiver control scisr td/ tc rd/ id/ or/ nf fe pe sci interrupt control scicr1 r8 t8 sc/ m wa/ pce ps pie received data register (rdr) receive shift register read transmit data register (tdr) transmit shift register write rdi tdo data register (scidr) transmitter clock receiver clock f cpu /ldiv sbk rw/ re te ilie rie tcie tie scicr2 lin slave baud rate auto synchronization unit f cpu scicr3 li/ la/ lhie lsf lh/ extended prescaler conventional baud rate generator and /16 scibrr lpr7 lpr0 lin slave baud rate generator 0 1 ld/ lhdm lhe lslv id ke transmit control up u re rf le um ne se df
on-chip peripherals st7l34, st7l35, st7l38, st7l39 146/236 doc id 11928 rev 7 additionally, an automatic resynchronization feature can be activated to compensate for any clock deviation, for more details please refer to lin baud rate on page 150 . lin header handling by a slave depending on the lin hea der detection method the linsci will signal the detection of a lin header after the lin synch break or after the identifier has been successfully received. note: 1 it is recommended to combine the header detection function with mute mode. putting the linsci in mute mode allows the detection of headers only and prevents the reception of any other characters. 2 this mode can be used to wait for the next header without being interrupted by the data bytes of the current message in case this message is not relevant for the application. synch break detection (lhdm = 0) when a lin synch break is received: the rdrf bit in the scisr register is set. it indicates that the content of the shift register is transferred to the scidr register , a value of 0x00 is expected for a break. the lhdf flag in the scicr3 register indicates that a lin synch break field has been detected. an interrupt is generated if the lhie bit in the scicr3 register is set and the i[1:0] bits are cleared in the ccr register. then the lin synch field is received and measured. ? if automatic resynchronization is enabled (lase bit = 1), the lin synch field is not transferred to the shift register: there is no need to clear the rdrf bit. ? if automatic resynchronization is disabled (lase bit = 0), the lin synch field is received as a normal character and transferred to the scidr register and rdrf is set. note: in lin slave mode, the fe bit detects all frame error which does not correspond to a break. identifier detection (lhdm = 1): this case is the same as the previous one except that the lhdf and the rdrf flags are set only after the entire header has been received (this is true whether automatic resynchronization is enabled or not). this indicates that the lin identifier is available in the scidr register. note: during lin synch field measurement, the sci state machine is switched off and no characters are transferred to the data register. lin slave parity in lin slave mode (line and lslv bits are set) lin parity checking can be enabled by setting the pce bit. in this case, the parity bits of the lin identifier field are checked. the identifier character is recognized as the third received character after a break character (included). see figure 61: lin header on page 147 .
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 147/236 figure 61. lin header the bits involved are the two msb positions (7th and 8th bits if m = 0; 8th and 9th bits if m = 0) of the identifier character. the check is performed as specified in figure 62 by the lin specification. figure 62. lin identifier lin error detection lin header error flag the lin header error flag indicates that an invalid lin header has been detected. when a lin header error occurs: the lhe flag is set an interrupt is generated if the rie bit is set and the i[1:0] bits are cleared in the ccr register. if autosynchronization is enabled (lase bit = 1), this can me an that the lin synch field is corrupted, and that the sci is in a blocked state (lsf bit is set). the only way to recover is to reset the lsf bit and then to clear the lhe bit. the lhe bit is reset by an access to the scisr register followed by a read of the scidr register. lhe/ovr error conditions when auto resynchronization is disabled (lase bit = 0), the lhe flag detects: that the received lin synch field is not equal to 55h. that an overrun occurred (as in standard sci mode) furthermore, if lhdm is set it also detects that a lin header reception timeout occurred (only if lhdm is set). lin synch lin synch identifier parity bits field field break identifier field parity bits id0 start bit stop bit id1 id2 id3 id4 id5 p0 p1 identifier bits p1 id1 id3 id4 id5 = p0 id0 = id1 id2 id4 m=0
on-chip peripherals st7l34, st7l35, st7l38, st7l39 148/236 doc id 11928 rev 7 when the lin auto-resynchronization is enabled (lase bit = 1), the lhe flag detects: that the deviation error on the synch field is outside the lin specif ication which allows up to 15.5% of period deviat ion between the slave an d master oscillators. a lin header reception timeout occurred. if t header > t header_max then the lhe flag is set. refer to figure 63 (only if lhdm is set to 1). an overflow during the synch field measurement, which leads to an overflow of the divider registers. if lhe is set due to this error then the sci goes into a blocked state (lsf bit is set). that an overrun occurred on fields other than the synch field (as in standard sci mode) deviation error on the synch field the deviation error is checked by comparing the current baud rate (relative to the slave oscillator) with the received lin synch field (relative to the mast er oscillator). two checks are performed in parallel: the first check is based on a measurement between the first fallin g edge and the last falling edge of the synch field. let us refer to this period deviation as d: if the lhe flag is set, it means that d > 15.625% if lhe flag is not set, it means that d < 16.40625% if 15.625% d < 16.40625%, then the flag can be either set or reset depending on the dephasing between the signal on the rdi line and the cpu clock. the second check is based on the measurement of each bit time between both edges of the synch field. this checks that each of these bit times is large enough compared to the bit time of the current baud rate. when lhe is set due to this error then the sci goes into a blocked state (lsf bit is set). lin header time-out error when the lin identifier field detection method is used (by configuring lhdm to 1) or when lin auto-resynch ronization is enabled (lase bit = 1), the linsci automatically monitors the t header_max condition given by the lin protocol. if the entire header (up to and including the stop bit of the lin identifier field) is not received within the maximum time limit of 57 bit times then a lin header error is signalled and the lhe bit is set in the scisr register. figure 63. lin header reception timeout the time-out counter is enabled at each break detection. it is stopped in the following conditions: t header lin synch lin synch identifier field field break
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 149/236 1. a lin identifier field has been received 2. an lhe error occurred (other than a timeout error) 3. a software reset of lsf bit (transition from high to low) occurred during the analysis of the lin synch field 4. if lhe bit is set due to th is error during the lin synchr field (if lase bit = 1) then the sci goes into a blocked state (lsf bit is set) if lhe bit is set due to this erro r during fields other than lin syn ch field or if lase bit is reset then the current received header is discarded and the sci searches for a new break field. note on lin header time-out limit according to the lin specification, the maximum length of a lin header which does not cause a timeout is equal to 1.4 * (34 + 1) = 49 t bit_master . t bit_master refers to the master baud rate. when checking this timeout, the slave node is desynchronized for the reception of the lin break and synch fields. consequently, a margin must be allowed, taking into account the worst case: this occurs when the lin identifier lasts exactly 10 t bit_master periods. in this case, the lin break and synch fields lasts 49 - 10 = 39 t bit_master periods. assuming the slave measures these first 39 bits with a desynchronized clock of 15.5%. this leads to a maximum allowed header length of: 39 x (1/0.845) t bit_master + 10t bit_master = 56.15 t bit_slave . a margin is provided so that the time-out occurs when the header length is greater than 57 t bit_slave periods. if it is less than or equal to 57 t bit_slave periods, then no timeout occurs. lin header length even if no timeout occurs on the lin header, it is possible to have access to the effective lin header length (t header ) through the lhl register. this allows monitoring at software level the t frame_max condition given by the lin protocol. this feature is only av ailable when lhdm bit = 1 or when lase bit = 1. mute mode and errors in mute mode when lhdm bit = 1, if an lhe error occurs during the analysis of the lin synch field or if a lin header time-out occurs then the lhe bit is set but it does not wake up from mute mode. in this case, the current header analysis is discarded. if needed, the software has to reset lsf bit. then the sci searches for a new lin header. in mute mode, if a framing error occurs on a data (which is not a break), it is discarded and the fe bit is not set. when lhdm bit = 1, any lin header which respects the following conditions causes a wake- up from mute mode: a valid lin break field (at least 11 dominant bits followed by a recessive bit) a valid lin synch field (without deviation error) a lin identifier field without framing error. note that a lin parity error on the lin identifier field does not prevent wake-up from mute mode. no lin header time-out should occur during header reception.
on-chip peripherals st7l34, st7l35, st7l38, st7l39 150/236 doc id 11928 rev 7 figure 64. lin synch field measurement lin baud rate baud rate programming is done by writing a value in the lpr prescaler or performing an automatic resynchronization as described below. automatic resynchronization to automatically adjust the baud rate based on measurement of the lin synch field: write the nominal lin prescaler value (usually depending on the nominal baud rate) in the lpfr/lpr registers set the lase bit to enable t he auto synchr onization unit when auto synchronization is enabled, after each lin synch break, the time duration between five falling edges on rdi is sampled on f cpu and the result of this measurement is stored in an internal 15-bit register called sm (not user accessible) (see figure 64 ). then the ldiv value (and its associated lpfr and lpr registers) are automatically updated at the end of the fifth falling edge. during lin synch field measurement, the sci state machine is stopped and no data is transferred to the data register. lin slave baud rate generation in lin mode, transmission and reception are driven by the lin baud rate generator note: lin master mode uses the extended or conventional prescaler register to generate the baud rate. if line bit = 1 and lslv bit = 1 then the conventional and extended baud rate generators are disabled the baud rate for the receiver and transmitter are both set to the same value, depending on the lin slave baud rate generator: where: ldiv is an unsigned fixed point number. the mantissa is coded on 8 bits in the lpr register and the fraction is coded on 4 bits in the lpfr register. if lase bit = 1 then ldiv is automatically updated at the end of each lin synch field. lin synch break extra ?1? bit0 bit1 start bit stop bit next start bit lin synch field measurement = 8.t br =sm.t cpu lpr(n) lpr(n+1) lpr = t br /(16.t cpu ) = rounding (sm/128) t cpu = cpu period t br = baud rate period t br sm = synch measurement register (15 bits) t br = 16.lp.t cpu bit2 bit3 bit4 bit5 bit6 bit7 tx = rx = (16 * ldiv) f cpu
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 151/236 three registers are used internally to manage the auto-update of the lin divider (ldiv): ldiv_nom (nominal value written by software at lpr/lpfr addresses) ldiv_meas (results of the field synch measurement) ldiv (used to generate the local baud rate) the control and interactions of these registers, explained in figure 65 and figure 66 , depend on the ldum bit setting (lin divider update method). note: as explained in figure 65 and figure 66 , ldiv can be updated by two concurrent actions: a transfer from ldiv_meas at the end of the lin sync field and a transfer from ldiv_nom due to a software write of lpr. if both operations occur at the same time, the transfer from ldiv_nom has priority. figure 65. ldiv read/write operations when ldum = 0 mant(7:0) ldiv frac(3:0) ldiv_nom baud rate generation read lpr write lpfr update at end of synch field frac(3:0) mant(7:0) ldiv_meas frac(3:0) mant(7:0) write lpr read lpfr lin sync field measurement write lpr
on-chip peripherals st7l34, st7l35, st7l38, st7l39 152/236 doc id 11928 rev 7 figure 66. ldiv read/write operations when ldum = 1 linsci clock tolerance linsci clock tolerance when unsynchronized when lin slaves are unsynchronized (meaning no characters have been transmitted for a relatively long time), the maximum tolerated deviation of the linsci clock is 15%. if the deviation is within this range then the lin synch break is detected properly when a new reception occurs. this is made possible by the fact that masters send 13 low bits for the lin synch break, which can be interpreted as 11 low bits (13 bits -15% = 11.05) by a ?fast? slave and then considered as a lin synch break. according to the lin specification, a lin synch break is valid when its duration is greater than t sbrkts = 10. this means that the lin synch break must last at least 11 low bits. note: if the period desynchronization of the slave is +15% (slave too slow), the character ?00h? which represents a sequence of 9 low bits must not be interpreted as a break character (9 bits + 15% = 10.35). consequently, a valid lin synch break must last at least 11 low bits. linsci clock tolerance when synchronized when synchronization has been performed, following reception of a lin synch break, the linsci, in lin mode, has the same clock devi ation tolerance as in sci mode, which is explained below: during reception, each bit is oversampled 16 times. the mean of the 8th, 9th and 10th samples is considered as the bit value. consequently, the clock frequency should not vary more than 6/16 (37.5%) within one bit. the sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation should not exceed 3.75%. rdrf = 1 write lpr write lpfr ldiv_nom frac(3:0) mant(7:0) lin sync field measurement update at end of synch field mant(7:0) frac(3:0) ldiv_meas mant(7:0) ldiv frac(3:0) baud rate generation read lpr read lpfr
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 153/236 clock deviation causes the causes which contribute to the total deviation are: ?d tra : deviation due to transmitter error. note: the transmitter can be either a master or a slave (in case of a slave listening to the response of another slave) ?d meas : error due to the lin synch measurement performed by the receiver ?d quant : error due to the baud rate quantization of the receiver ?d rec : deviation of the local o scillator of the re ceiver. this deviation can occur during the reception of one complete lin message assuming that the deviation has been compensated at the beginning of the message. ?d tcl : deviation due to the transmission line (generally due to the transceivers) all the deviations of the system should be added and compared to the linsci clock tolerance: d tra + d meas +d quant + d rec + d tcl < 3.75% figure 67. bit sampling in reception mode error due to lin synch measurement the lin synch field is measured over eight bit times. this measurement is performed using a counter clocked by the cpu clock. the edge detections are performed using the cpu clock cycle. this leads to a precision of 2 cpu clock cyc les for the measurement which lasts 16*8*ldiv clock cycles. consequently, this error (d meas ) is equal to: 2/(128*ldiv min ). ldiv min corresponds to the minimum lin prescaler content, leading to the maximum baud rate, taking into account the maximum deviation of +/-15%. error due to baud rate quantization the baud rate can be adjusted in steps of 1/(16 * ldiv). the worst case occurs when the ?real? baud rate is in the middle of the step. this leads to a quantization error (d quant ) equal to 1/(2*16*ldiv min ). rdi line sample 123456789101112131415 16 sampled values one bit time 6/16 7/16 7/16 clock
on-chip peripherals st7l34, st7l35, st7l38, st7l39 154/236 doc id 11928 rev 7 impact of clock deviation on maximum baud rate the choice of the nominal baud rate (ldiv nom ) will influence both the quantization error (d quant ) and the measurement error (d meas ). the worst case occurs for ldiv min . consequently, at a given cpu frequency, the maximum possible nominal baud rate (lpr min ) should be chosen with respect to the maximum tolerated deviation given by the equation: d tra + 2 / (128*ldiv min ) + 1 / (2*16*ldiv min ) + d rec + d tcl < 3.75% example: a nominal baud rate of 20 kbits/s at t cpu = 125ns (8 mhz) leads to ldiv nom = 25d ldiv min = 25 - 0.15*25 = 21.25 d meas = 2 / (128*ldiv min ) * 100 = 0.00073% d quant = 1 / (2*16*ldiv min ) * 100 = 0.0015%. lin slave systems for lin slave systems (the line and lslv bits are set), receivers wake up by lin synch break or lin identifier detection (depending on the lhdm bit). hot plugging feature for lin slave nodes in lin slave mute mode (the line, lslv and rwu bits are set) it is possible to hot plug to a network during an ongoing communication flow. in this case the sci monitors the bus on the rdi line until 11 consecutive dominant bits have been detected and discards all the other bits received. 11.5.10 lin mode register description status register (scisr) scisr reset value: 1100 0000 (c0h) 76543210 tdre tc rdrf idle lhe nf fe pe ro ro ro ro ro ro ro ro
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 155/236 table 70. scisr register description (1) bit name function 7 tdre transmit data register empty this bit is set by hardware when the cont ent of the tdr register has been transferred into the shift register. an interrupt is genera ted if the tie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register 6tc transmission complete this bit is set by hardware when transm ission of a character containing data is complete. an interrupt is generated if tcie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a preamble or a break. 5rdrf received data ready flag this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interrupt is gener ated if rie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data are ready to be read 4idle idle line detected this bit is set by hardware when an idle li ne is detected. an interrupt is generated if the ilie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit is not set again until the rdrf bit has been set itself (that is, a new idle line occurs). 3lhe lin header error during lin header this bit signals three error types: the lin synch field is corrupted and the sci is blocked in lin synch state (lsf bit = 1). a timeout occurred during lin header reception. an overrun error was detected on one of the header field (see or bit description in status register (scisr) on page 135 ). an interrupt is generated if rie = 1 in the sc icr2 register. if blocked in the lin synch state, the lsf bit must first be reset (to exit lin synch field state and then to be able to clear lhe flag). then it is cleared by the following software sequence: an access to the scisr register followed by a read to the scidr register. 0: no lin header error 1: lin header error detected note: apart from the lin header this bit signals an overrun error as in sci mode, (see description in status register (scisr) on page 135 ).
on-chip peripherals st7l34, st7l35, st7l38, st7l39 156/236 doc id 11928 rev 7 control register 1 (scicr1) 2nf noise flag in lin master mode (line bit = 1 and lslv bit = 0) this bit has the same function as in sci mode, please refer to status register (scisr) on page 135 . in lin slave mode (line bit = 1 and lslv bit = 1) this bit has no meaning. 1fe framing error in lin slave mode, this bit is set only when a real framing error is detected (if the stop bit is dominant (0) and at least one of the other bits is recessive (1). it is not set when a break occurs, the lhdf bit is used instead as a break flag (if the lhdm bit = 0). it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error 1: framing error detected 0pe parity error this bit is set by hardware when a lin parity error occurs (if the pce bit is set) in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an interrupt is generated if pie = 1 in the scicr1 register. 0: no lin parity error 1: lin parity error detected 1. bits 7:4 have the same function as in sci mode, please refer to status register (scisr) on page 135 . scicr1 reset value: x000 0000 (x0h) 76543210 r8 t8 scid m wake pce reserved pie r/w r/w r/w r/w r/w r/w - r/w table 71. scicr1 register description (1) bit name function 7 r8 receive data bit 8 this bit is used to store the 9th bit of the received word when m = 1. 6t8 transmit data bit 8 this bit is used to store the 9th bit of the transmitted word when m = 1. 5scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled table 70. scisr register description (1) (continued) bit name function
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 157/236 control register 2 (scicr2) 4m word length this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note: the m bit must not be modified during a data transfer (both transmission and reception). 3wake wake-up method this bit determines the sci wake-up method. it is set or cleared by software. 0: idle line 1: address mark note: if the line bit is set, the wake bit is deactivated and repl aced by the lhdm bit. 2pce parity control enable this bit is set and cleared by software. it selects the hardware parity control for lin identifier parity check. 0: parity control disabled 1: parity control enabled when a parity error occurs, the pe bit in the scisr register is set. 1 - reserved, must be kept cleared 0pie parity interrupt enable this bit enables the interrupt capability of the hardware parity control when a parity error is detected (pe bit set). the parity error involved can be a byte parity error (if bit pce is set and bit lpe is reset) or a lin parity error (if bit pce is set and bit lpe is set). 0: parity error interrupt disabled 1: parity error interrupt enabled 1. bits 7:3 and bit 0 have the same functi on as in sci mode; please refer to control register 1 (scicr1) on page 137 . scicr2 reset value: 0000 0000 (00h) 76543210 tie tcie rie ilie te re rwu sbk r/w r/w r/w r/w r/w r/w r/w r/w table 71. scicr1 register description (1) (continued) bit name function
on-chip peripherals st7l34, st7l35, st7l38, st7l39 158/236 doc id 11928 rev 7 table 72. scicr2 register description (1) 1. bits 7:2 have the same function as in sci mode; please refer to control register 2 (scicr2) on page 138 . bit name function 7 tie transmitter interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre = 1 in the scisr register 6tcie transmission complete interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc = 1 in the scisr register 5rie receiver interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or = 1 or rdrf = 1 in the scisr register 4ilie idle line interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle = 1 in the scisr register 3te transmitter enable this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled note: during transmission, a ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. when te is set, there is a 1 bit-time delay before the transmission starts. 2re receiver enable this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled in the scisr register 1: receiver is enabled and begins searching for a start bit 1rwu receiver wake-up this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: mute mode is recommended for detecting only the header and avoiding the reception of any other characters. for more details please refer to lin reception on page 145 . in lin slave mode, when rdrf is set, the software can not set or clear the rwu bit. 0 sbk send break this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1? and then to ?0?, the tran smitter sends a break word at the end of the current word.
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 159/236 control register 3 (scicr3) scicr3 reset value: 0000 0000 (00h) 76543210 ldum line lslv lase lhdm lhie lhdf lsf r/w r/w r/w r/w r/w r/w r/w r/w table 73. scicr3 register description bit name function 7 ldum lin divider update method this bit is set and cleared by software and is also cleared by hardware (when rdrf = 1). it is only used in lin slave mode. it determines how the lin divider can be updated by software. 0: ldiv is updated as soon as lpr is written (if no auto synchronization update occurs at the same time) 1: ldiv is updated at the next received character (when rdrf = 1) after a write to the lpr register note: if no write to lpr is performed bet ween the setting of ldum bit and the reception of the next character, ld iv is updated with the old value. after ldum has been set, it is possible to reset the ldum bit by software. in this case, ldiv can be modified by writing into lpr/lpfr registers. 6:5 line, lslv lin mode enable bits these bits configure the lin mode: 0x: lin mode disabled 10: lin master mode 11: lin slave mode the lin master configuration enables sending of lin synch breaks (13 low bits) using the sbk bit in the scicr2 register. the lin slave configuration enables: the lin slave baud rate gener ator. the lin divider (ldiv) is then represented by the lpr and lpfr registers. the lp r and lpfr registers are read/write accessible at the address of the scib rr register and the address of the scietpr register. management of lin headers lin synch break detection (11-bit dominant) lin wake-up method (see lhdm bit) instead of the normal sci wake-up method inhibition of break transmission capability (sbk has no effect) lin parity checking (in conjunction with the pce bit) 4 lase lin auto synch enable this bit enables the auto synch unit (asu). it is set and cleared by software. it is only usable in lin slave mode. 0: auto synch unit disabled 1: auto synch unit enabled
on-chip peripherals st7l34, st7l35, st7l38, st7l39 160/236 doc id 11928 rev 7 figure 68. lsf bit set and clear 3lhdm lin header detection method this bit is set and cleared by software. it is only usable in lin slave mode. it enables the header detection method. in ad dition if the rwu bit in the scicr2 register is set, the lhdm bit select s the wake-up method (replacing the wake bit). 0: lin synch break detection method 1: lin identifier field detection method 2lhie lin header interrupt enable this bit is set and cleared by software. it is only usable in lin slave mode. 0: lin header interrupt is inhibited 1: an sci interrupt is generated whenever lhdf = 1 1 lhdf lin header detection flag this bit is set by hardware when a lin header is detected and cleared by a software sequence (an access to the scisr register followed by a read of the scicr3 register). it is only usable in lin slave mode. 0: no lin header detected 1: lin header detected note: the header detection method depends on the lhdm bit: - if lhdm = 0, a header is detected as a lin synch break - if lhdm = 1, a header is detected as a lin identifier, meaning that a lin synch break field + a lin synch field + a lin identifier field have been consecutively received. 0lsf lin synch field state this bit indicates that the lin synch field is being analyzed. it is only used in lin slave mode. in auto synchronization mode (lase bit = 1), when the sci is in the lin synch field state it waits or counts the falling edges on the rdi line. it is set by hardware as soon as a lin synch break is detected and cleared by hardware when the lin synch fi eld analysis is finished (see figure 68 ). this bit can also be cleared by software to exit lin synch state and return to idle mode. 0: the current character is not the lin synch field 1: lin synch field state (lin synch field undergoing analysis) table 73. scicr3 register description (continued) bit name function lin synch lin synch identifier parity bits field field break 11 dominant bits lsf bit
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 161/236 lin divider registers ldiv is coded using the two registers lpr and lpfr. in lin slave mode, the lpr register is accessible at the address of the scibrr register and the lpfr register is accessible at the address of the scietpr register. lin prescaler register (lpr) caution: lpr and lpfr registers have different meanings when reading or writing to them. consequently bit manipulation in structions (bres or bset) should never be used to modify the lpr[7:0] bits, or the lpfr[3:0] bits. lin prescaler fraction register (lpfr) lpr reset value: 0000 0000 (00h) 76543210 lpr[7:0] r/w table 74. lpr register description bit name function 7:0 lpr[7:0] lin prescaler (mantissa of ldiv) these 8 bits define the value of the mantissa of the ldiv (see ta bl e 7 5 ). table 75. lin mantissa rounded values lpr[7:0] rounded mantissa (ldiv) 00h sci clock disabled 01h 1 ... ... feh 254 ffh 255 lpfr reset value: 0000 0000 (00h) 76543210 reserved lpfr[3:0] -r/w
on-chip peripherals st7l34, st7l35, st7l38, st7l39 162/236 doc id 11928 rev 7 examples of ldiv coding example 1: lpr = 27d and lpfr = 12d this leads to: mantissa (ldiv) = 27d fraction (ldiv) = 12/16 = 0.75d therefore ldiv = 27.75d example 2: ldiv = 25.62d this leads to: lpfr = rounded(16*0.62d) = rounded(9.92d) = 10d = ah lpr = mantissa (25.620d) = 25d = 1bh example 3: ldiv = 25.99d this leads to: lpfr = rounded(16*0.99d) = rounded(15.84d) = 16d the carry must be propagated to the mantissa: lpr = mantissa (25.99) + 1=26d=1ch. lin header length register (lhlr) table 76. lpfr register description bit name function 7:4 - reserved, must be kept cleared 3:0 lpfr[3:0] fraction of ldiv these 4 bits define the fraction of the ldiv (see ta b l e 7 7 ). note: when initializing ldiv, the lpfr regi ster must be written first. then, the write to the lpr register effectively updates ldiv and so the clock generation. in lin slave mode, if the lpr[7:0] regi ster is equal to 00h, the transceiver and receiver input clocks are switched off. table 77. ldiv fractions lpfr[3:0] fraction (ldiv) 0h 0 1h 1/16 ... ... eh 14/16 fh 15/16 lhlr reset value: 0000 0000 (00h) 76543210 lhl[7:0] r
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 163/236 note: in lin slave mode when lase = 1 or lhdm = 1, the lhlr register is accessible at the address of the scierpr register. otherwise this register is always read as 00h. table 78. lhlr register description bit name function 7:0 lhl[7:0] lin header length this is a read-only register, which is u pdated by hardware if one of the following conditions occurs: after each break detection , it is loaded with ?ffh? if a timeout occurs on t header , it is loaded with 00h after every successful lin header receptio n (at the same time as the setting of lhdf bit), it is loaded with a value (lhl) which gives access to the number of bit times of the lin header length (t header ). lhl register coding is as follows: t header_max =57 lhl (7:2) represents the mantissa of (57 - t header ) (see ta b l e 7 9 ) lhl (1:0) represents the fraction (57 - t header ) (see ta bl e 8 0 ) table 79. lin header mantissa values lhl[7:2] mantissa (57 - t header ) mantissa ( t header ) 0h 0 57 1h 1 56 ... ... ... 39h 56 1 3ah 57 0 3bh 58 never occurs ... ... ... 3eh 62 never occurs 3fh 63 initial value table 80. lin header fractions lhl[1:0] fraction (57 - t header ) 0h 0 1h 1/4 2h 1/2 3h 3/4
on-chip peripherals st7l34, st7l35, st7l38, st7l39 164/236 doc id 11928 rev 7 examples of lhl coding: example 1: lhl = 33h = 001100 11b lhl(7:3) = 1100b = 12d lhl(1:0) = 11b = 3d this leads to: mantissa (57 - t header )=12d fraction (57 - t header ) = 3/4 = 0.75 therefore: (57 - t header ) = 12.75d and t header = 44.25d example 2: 57 - t header = 36.21d lhl(1:0) = rounded(4*0.21d) = 1d lhl(7:2) = mantissa (36.21d) = 36d = 24h therefore lhl(7:0) = 10010001 = 91h example 3: 57 - t header = 36.90d lhl(1:0) = rounded(4*0.90d) = 4d the carry must be propagated to the matissa: lhl(7:2) = mantissa (36.90d) + 1 = 37d therefore lhl(7:0) = 10110000 = a0h table 81. linsci1 register map and reset values addr. (hex.) register name 7 6 5 4 3 2 1 0 40 scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or/lhe 0 nf 0 fe 0 pe 0 41 scidr reset value dr7 - dr6 - dr5 - dr4 - dr3 - dr2 - dr1 - dr0 - 42 scibrr lpr (lin slave mode) reset value scp1 lpr7 0 scp0 lpr6 0 sct2 lpr5 0 sct1 lpr4 0 sct0 lpr3 0 scr2 lpr2 0 scr1 lpr1 0 scr0 lpr0 0 43 scicr1 reset value r8 x t8 0 scid 0 m 0 wake 0 pce 0 ps 0 pie 0 44 scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 45 scicr3 reset value np 0 line 0 lslv 0 lase 0 lhdm 0 lhie 0 lhdf 0 lsf 0 46 scierpr lhlr (lin slave mode) reset value erpr7 lhl7 0 erpr6 lhl6 0 erpr5 lhl5 0 erpr4 lhl4 0 erpr3 lhl3 0 erpr2 lhl2 0 erpr1 lhl1 0 erpr0 lhl0 0 47 scitpr lpfr (lin slave mode) reset value etpr7 ldum 0 etpr6 0 0 etpr5 0 0 etpr4 0 0 etpr3 lpfr3 0 etpr2 lpfr2 0 etpr1 lpfr1 0 etpr0 lpfr0 0
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 165/236 11.6 10-bit a/d converter (adc) 11.6.1 introduction the on-chip analog to digital converter (adc) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. this peripheral has up to seven multiplexed analog input channels (refer to device pinout description) that allow the peripheral to convert the analog voltage levels from up to seven different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 11.6.2 main features 10-bit conversion up to 7 channels with multiplexed input linear successive approximation data register (dr) whic h contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 69: adc block diagram on page 166 . 11.6.3 functional description analog power supply v dda and v ssa are the high and low level reference voltage pins. in some devices (refer to section 2: pin description ) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. 40 scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or/lhe 0 nf 0 fe 0 pe 0 41 scidr reset value dr7 - dr6 - dr5 - dr4 - dr3 - dr2 - dr1 - dr0 - table 81. linsci1 register map and reset values (continued) addr. (hex.) register name 7 6 5 4 3 2 1 0
on-chip peripherals st7l34, st7l35, st7l38, st7l39 166/236 doc id 11928 rev 7 figure 69. adc block diagram digital a/d conversion result the conversion is monotonic, meaning that the result never decreases if the analog input does not decrease and never increases if the analog input does not increase. if the input voltage (v ain ) is greater than v dda (high-level voltage reference) then the conversion result is ffh in the adcdrh register and 03h in the adcdrl register (without overflow indication). if the input voltage (v ain ) is lower than v ssa (low-level voltage reference) then the conversion result in the adcdrh an d adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conv ersion is stored in the adcdrh and adcdrl registers. the accuracy of the conversion is described in the section 13: electrical characteristics . r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this results in a loss of accuracy due to leakage and sampling not being completed in the alloted time. a/d conversion the analog input ports must be configured as input, no pull-up, no interrupt. refer to section 10: i/o ports . using these pins as analog inputs d oes not affect the ability of the port to be read as a logic input. in the adccsr register, select the ch[2:0] bits to assign the analog channel to convert. ch2 ch1 eoc spe ad 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 3 d1 d0 adcdrl 00 0 amp amp 0 r adc c adc hold control sel f adc f cpu 0 1 1 0 div 2 div 4 slow bit cal ed on sl ow
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 167/236 adc conversion mode in the adccsr register, set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: ? the eoc bit is set by hardware ? the result is in the adcdr registers a read to the adcdrh resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll the eoc bit 2. read adcdrl 3. read adcdrh. this clears eoc automatically to read only 8 bits, perform the following steps: 1. poll eoc bit 2. read adcdrh. this clears eoc automatically 11.6.4 low-power modes note: the a/d converter may be disabled by resetting the adon bit. this feature allows reduced power consumption when no conversion is needed and between single shot conversions . 11.6.5 interrupts none. table 82. effect of low power modes on the a/d converter mode description wait no effect on a/d converter halt a/d converter disabled after wakeup from halt mode, the a/d converter requires a stabilization time t stab ( section 13: electrical characteristics ) before accurate conversions can be performed.
on-chip peripherals st7l34, st7l35, st7l38, st7l39 168/236 doc id 11928 rev 7 11.6.6 register description control/status register (adccsr) adccsr reset value: 0000 0000 (00h) 76543210 eoc speed adon reserved reserved ch[2:0] r r/w r/w - - r/w table 83. adccsr regi ster description bit bit name function 7eoc end of conversion this bit is set by hardware. it is cleared by software reading the adcdrh register. 0: conversion is not complete 1: conversion complete 6 speed adc clock selection this bit is set and cleared by software. it is used together with the slow bit to configure the adc clock speed. refer to table 86: adc clock configuration on page 169 concerning the slow bit description of the adcdrl register. 5adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on 4:3 - reserved, must be kept cleared. 2:0 ch[2:0] channel selection these bits are set and cleared by software. they select the analog input to convert: 000: channel pin = ain0 001: channel pin = ain1 010: channel pin = ain2 011: channel pin = ain3 100: channel pin = ain4 101: channel pin = ain5 110: channel pin = ain6 note: the number of channels is device dependent. refer to section 2: pin description.
st7l34, st7l35, st7l38, st7l39 on-chip peripherals doc id 11928 rev 7 169/236 data register high (adcdrh) control and data register low (adcdrl) adcdrh reset value: 0000 0000 (00h) 76543210 d[9:2] r table 84. adcdrh regi ster description bit bit name function 7:0 d[9:2] msb of analog converted value adcdrl reset value: 0000 0000 (00h) 76543210 reserved reserved reserved reserved slow reserved d[1:0] ----r/w- r/w table 85. adcdrl register description bit bit name function 7:5 - reserved, must be kept cleared 4 - reserved, must be kept cleared 3slow slow mode this bit is set and cleared by software. it is used together with the speed bit to configure the adc clock speed as shown in ta b l e 8 6 : adc clock configuration on page 169 2 - reserved, must be kept cleared 1:0 d[1:0] lsb of converted analog value table 86. adc clock configuration (1) 1. max f adc allowed = 4 mhz (see section 13.11: 10-bit adc characteristics on page 212 ) f adc slow speed f cpu /2 0 0 f cpu 01 f cpu /4 1 x
on-chip peripherals st7l34, st7l35, st7l38, st7l39 170/236 doc id 11928 rev 7 table 87. adc register map and reset values address (hex.) register label 76 5 4 3 2 10 0034h adccsr reset value eoc 0 speed 0 adon 0 0 0 0 0 ch2 0 ch1 0 ch0 0 0035h adcdrh reset value d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 0036h adcdrl reset value 0 0 0 0 0 0 0 0 slow 0 0 0 d1 x d0 x
st7l34, st7l35, st7l38, st7l39 instruction set doc id 11928 rev 7 171/236 12 instruction set 12.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in seven main groups (see ta b l e 8 8 ). the st7instruction set is designed to minimize the number of bytes required per instruction. to do so, most of the addressing modes may be subdivided in two sub-modes called long and short: long addressing mode is more powerful because it can use the full 64 kbyte address space, however it uses more bytes and more cpu cycles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory instructions use shor t addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 88. cpu addressing mode groups addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5
instruction set st7l34, st7l35, st7l38, st7l39 172/236 doc id 11928 rev 7 table 89. cpu addressing mode overview mode syntax destination/s ource pointer address pointer size length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) +1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a, ($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 000 0..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10. w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc- 128/pc+127 (1) 1. at the time the instruction is executed, the program counter (pc) points to the instruction following jrxx. + 1 relative indirect jrne [$10] pc- 128/pc+127 (1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3
st7l34, st7l35, st7l38, st7l39 instruction set doc id 11928 rev 7 173/236 12.1.1 inherent all inherent instructions consis t of a single byte. the opcode fully specifies all the required information for the cpu to process the operation. 12.1.2 immediate immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. table 90. inherent instructions inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret subroutine return iret interrupt subroutine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc sh ift and rotate operations swap swap nibbles table 91. immediate instructions immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
instruction set st7l34, st7l35, st7l38, st7l39 174/236 doc id 11928 rev 7 12.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub-modes: direct instructions (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff addressing space. direct instructions (long) the address is a word, thus allowing 64 kbyte addressing space, but requires two bytes after the opcode. 12.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte after the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte addressing space and requires two bytes after the opcode. 12.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (pointer). the pointer address follows the opcode. the indirect addressing mode consists of two sub- modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode.
st7l34, st7l35, st7l38, st7l39 instruction set doc id 11928 rev 7 175/236 12.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (x or y) with a pointer value located in memory. the pointer address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 92. instructions supporting direct, i ndexed, indirect and indirect indexed addressing modes long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/substraction operations bcp bit compare table 93. short instructions and functions short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine
instruction set st7l34, st7l35, st7l38, st7l39 176/236 doc id 11928 rev 7 12.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub-modes: relative (direct) the offset follows the opcode relative (indirect) the offset is defined in memory, of which the address follows the opcode. 12.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 ma in groups as illustrated in ta b l e 9 5 . table 94. relative mode instructions (direct and indirect) available relative direct/i ndirect instructions function jrxx conditional jump callr call relative table 95. instruction groups load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf
st7l34, st7l35, st7l38, st7l39 instruction set doc id 11928 rev 7 177/236 12.2.1 using a prebyte the instructions are described with one to four bytes. in order to extend the number of available opcodes for an 8-bit cpu (256 opcodes), three different prebyte opcodes are defined. these prebytes modify the meaning of the instruction they precede. the whole instruction becomes: these prebytes enable instructions in y as well as indirect addressing modes to be implemented. they precede the opcode of the instructions in x or the instructions using direct addressing mode. the prebytes are: 12.2.2 illegal opcode reset in order to provide the devicewith enhanced robustness against unexpected behavior, a system of illegal opcode detection is implem ented. if a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. this, combined with the watchdog, allows the detection and recovery from an unexpected fault or interference. note: a valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset. pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address pdy 90 replaces an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one pix 92 replaces an instruction using direct, direct bit, or direct relative addressing mode by an instruction using the corresponding indirect addressing mode it also changes an instruction using x indexed addressing mode to an instruction using indirect x indexed addressing mode piy 91 replaces an instruction using x indirect indexed addressing mode by a y one
instruction set st7l34, st7l35, st7l38, st7l39 178/236 doc id 11928 rev 7 table 96. instruction set overview mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >=
st7l34, st7l35, st7l38, st7l39 instruction set doc id 11928 rev 7 179/236 jrugt jump if (c + z = 0) unsigned > jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z table 96. instruction set overview (continued) mnemo description function/example dst src h i n z c
electrical characteristics st7l34, st7l35, st7l38, st7l39 180/236 doc id 11928 rev 7 13 electrical characteristics 13.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 13.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a =t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 13.1.2 typical values unless otherwise specified, typical data are based on t a =25 c, v dd = 5 v (for the 4.5 v v dd 5.5 v voltage range) and v dd = 3.3 v (for the 3 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. 13.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 70 . figure 70. pin loading conditions c l st7 pin
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 181/236 13.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 71 . figure 71. pin input voltage 13.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in st7 pin
electrical characteristics st7l34, st7l35, st7l38, st7l39 182/236 doc id 11928 rev 7 13.2.1 voltage characteristics 13.2.2 current characteristics table 97. voltage characteristics symbol ratings maximum value unit v dd - v ss supply voltage 7.0 v v in input voltage on any pin (1)(2) 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guar antee safe operation, this connecti on must be made through a pull-up or pull-down resistor (typical: 4.7 k for reset , 10 k for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in v dd while a negative injection is induced by v in st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 183/236 13.2.3 thermal characteristics table 99. thermal characteristics symbol ratings value unit t stg storage temperature range -65 to +150 c t j maximum junction temperature (see table 129: thermal characteristics on page 216 )
electrical characteristics st7l34, st7l35, st7l38, st7l39 184/236 doc id 11928 rev 7 13.3 operating conditions 13.3.1 general operating conditions t a = -40 to +125 c unless otherwise specified. figure 72. f clkin maximum operating frequency vs v dd supply voltage 1. for further information on cloc k management block diagram for f clkin description, refer to figure 13: clock management block diagram on page 41 . table 100. general operating conditions symbol parameter co nditions min max unit v dd supply voltage f osc = 16 mhz max t a = -40c to t a max 3.0 5.5 v f clkin external clock frequency on clkin pin v dd = 3 to 3.3 v 0 8 mhz v dd = 3.3 to 5.5 v 0 16 mhz t a ambient temperature range a suffix version -40 +85 c c suffix version +125 f clkin [mhz] supply voltage [v] 16 8 4 1 0 2.0 2.7 3.3 3.5 4.0 4.5 5.0 functionality not guaranteed in this area 5.5 functionality guaranteed in this area (unless otherwise stated in the tables of parametric data) 3.0 refer to section 13.3.4: internal rc oscillator and pll for pll operating range
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 185/236 the rc oscillator and pll characte ristics are temper ature-dependent. table 101. operating conditions (tested for t a = -40 to +125 c) @ v dd = 4.5 to 5.5 v symbol parameter conditions flash rom unit min typ max min typ max f rc (1) 1. if the rc oscillator clock is selected, to improve clock stability and frequency ac curacy, it is recommended to place a decoupling capacitor, typically 100nf, between the v dd and v ss pins as close as possi ble to the st7 device. internal rc oscillator frequency rccr = ff (reset value), t a = 25 c, v dd =5 v 630 630 khz rccr = rccr0 (2) , t a = -40 to 125 c, v dd =5 v 2. see section 7.1: internal rc oscillator adjustment on page 38 930 1000 1050 tbd 1000 tbd acc rc rc resolution v dd =5 v -1 +1 tbd tbd % accuracy of internal rc oscillator with rccr = rccr0 (2)(3) 3. minimum value is obtained for hot temperature and maximum value is obtained for cold temperature t a = -40 to +125 c, v dd =5 v -3 +5 tbd tbd t a = -40 to +125 c, v dd = 4.5 v to 5.5 v (4) 4. data based on characterization results, not tested in production -4.5 +6.5 tbd tbd table 102. operating conditions (tested for t a = -40 to +125 c) @ v dd = 4.5 to 5.5 v symbol parameter conditions flash and rom unit min typ max i dd(rc) rc oscillator current consumption t a = 25 c, v dd =5 v 600 (1)(2) 1. measurement made with rc calibrated at 1 mhz 2. data based on characterization results, not tested in production a t su(rc) rc oscillator setup time 10 (3) 3. see section 7.1: internal rc oscillator adjustment on page 38 s f pll x8 pll input clock 1 mhz t lock pll lock time (4) 4. after the locked bit is set acc pll is maximum 10% until t stab has elapsed. see figure 12: pll output frequency timing diagram on page 39 . 2 ms t stab pll stabilization time (4) 4 acc pll x8 pll accuracy f clkin /2 or f rc =1 mhz @t a = -40 to +125 c 0.2 (5) 5. averaged over a 4ms period. after t he locked bit is set, a period of t stab is required to reach acc pll accuracy % jit pll pll jitter ( f cpu /f cpu )1 (6) 6. guaranteed by design i dd(pll) pll current consumption t a = 25 c 550 (2) a
electrical characteristics st7l34, st7l35, st7l38, st7l39 186/236 doc id 11928 rev 7 figure 73. typical accuracy with rccr = rccr0 vs v dd = 4.5 to 5.5 v and temperature figure 74. f rc vs v dd and temperature for calibrated rccr0 -1.00% -0.50% 0.00% 0.50% 1.00% 1.50% 2.00% 2.50% 3.00% 4.5 5 5.5 vdd (v) accuracy (%) -45c 0c 25c 90c 110c 130c rccr0 typical behavior 0.9 0.95 1 1.05 1.1 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 vdd supply (v) frequency (mhz) -45c' 0c' 25c' 90c' 110c' 130c' table 103. operating conditions (tested for t a = -40 to +125 c) @ v dd = 3.0 to 3.6 v symbol parameter conditions flash rom unit min typ max min typ max f rc (1) internal rc oscillator frequency rccr = ff (reset value), t a = 25 c, v dd = 3.3 v 630 630 khz rccr = rccr (2) , t a = -40 to +125 c, v dd = 3.3 v 970 1000 1050 tbd 1000 tbd
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 187/236 figure 75. typical accurac y with rccr = rccr1 vs v dd = 3 to 3.6 v and temperature acc rc rc resolution v dd = 3.3 v -1 +1 tbd tbd % accuracy of internal rc oscillator with rccr = rccr0 (2)(3) t a = -40 to +125 c, v dd = 3.3 v -3 +5 tbd tbd t a = -40 to +125 c, v dd = 3.0 v to 3.6 v (4) -4 +6 tbd tbd 1. if the rc oscillator clock is selected, to improve clock stability and frequency ac curacy, it is recommended to place a decoupling capacitor, typically 100nf, between the v dd and v ss pins as close as possi ble to the st7 device. 2. see section 7.1: internal rc oscillator adjustment on page 38 . 3. minimum value is obtained for hot temperatur e and max value is obtained for cold temperature. 4. data based on characterization results, not tested in production. table 104. operating conditions (tested for t a = -40 to +125 c) @ v dd = 3.0 to 3.6 v (1) 1. data based on characterization results, not tested in production. parameter (1) conditions flash and rom min typ max i dd(rc) rc oscillator current consumption t a = 25 c, v dd = 3.3 v 500 (2) 2. measurement made with rc calibrated at 1 mhz. a t su(rc) rc oscillator setup time 10 (2) s table 103. operating conditions (tested for t a = -40 to +125 c) @ v dd = 3.0 to 3.6 v symbol parameter conditions flash rom unit min typ max min typ max -1.00% -0.50% 0.00% 0.50% 1.00% 1.50% 33.33.6 vdd (v) accuracy (%) -45c 0c 25c 90c 110c 130c
electrical characteristics st7l34, st7l35, st7l38, st7l39 188/236 doc id 11928 rev 7 figure 76. f rc vs v dd and temperature for calibrated rccr1 figure 77. pll x 8 output vs clkin frequency 1. f osc = f clkin /2*pll8 13.3.2 operating conditions with low voltage detector (lvd) t a = -40 to +125 c, unless otherwise specified rccr1 typical behavior 0.9 0.95 1 1.05 1.1 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 vdd supply (v) frequency (mhz) -45c' 0c' 25c' 90c' 110c' 130c' 1.00 3.00 5.00 7.00 9.00 11.00 0.85 0.9 1 1.5 2 2.5 external input clock frequency (mhz) output frequency (mhz) 5.5 5 4.5 4 table 105. operating conditions with low voltage detector symbol parameter conditions (1) min typ max unit v it+ (lvd) reset release threshold (v dd rise) high threshold 3.60 (2) 4.15 4.50 v v it- (lvd) reset generation threshold (v dd fall) high threshold 3.40 3.95 4.40 (2)
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 189/236 v hys lvd voltage threshold hysteresis v it+ (lvd) -v it- (lvd) 200 mv vt por v dd rise time rate (3)(4) 20 (2) 10000 (2) s/v t g(vdd) filtered glitch delay on v dd not detected by the lvd 150 (5) ns i dd(lvd ) lvd/avd current consumption 200 a 1. lvd functionality guaranteed only within the v dd operating range specified in section 13.3.1: general operating conditions on page 184 . 2. not tested in production. 3. not tested in production. the v dd rise time rate condition is needed to insure a correct device power-on and lvd reset. when the v dd slope is outside these values, the lvd may not ensure a proper reset of the mcu. 4. use of lvd with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull v dd down to 0 v to ensure optimum restart conditions. refer to circuit example in figure 97: reset pin protection when lvd is disabled on page 208 . 5. based on design simulation. table 105. operating conditions with low voltage detector symbol parameter conditions (1) min typ max unit
electrical characteristics st7l34, st7l35, st7l38, st7l39 190/236 doc id 11928 rev 7 13.3.3 auxiliary voltage detector (avd) thresholds t a = -40 to +125c, unless otherwise specified 13.3.4 internal rc oscillator and pll the st7 internal clock can be supplied by an internal rc o scillator and pll (selectable by option byte). table 106. auxiliary voltage detector (avd) thresholds symbol parameter conditions (1) 1. lvd functionality guaranteed only within the v dd operating range specified in figure 70: pin loading conditions on page 180 min typ max unit v it + (avd) 1 = >0 avdf flag toggle threshold (v dd rise) high threshold 3.85 (2) 2. not tested in production 4.45 4.90 v v it - (avd) 0 = >1 avdf flag toggle threshold (v dd fall) high threshold 3.80 4.40 4.85 (2) v hys avd voltage threshold hysteresis v it + (avd) -v it - (avd) 150 mv v it- voltage drop between avd flag set and lvd reset activation v dd fall 0.45 v table 107. internal rc oscillator and pll symbol parameter conditions min typ max unit v dd(rc) internal rc oscillator operating voltage refer to operating range of v dd with t a, figure 70: pin loading conditions on page 180 3.0 5.5 v v dd(x8pll) x8 pll operating voltage 3.6 5.5
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 191/236 13.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to obtain the total device consumption, the two current values must be added (except for halt mode for which the clock is stopped). 13.4.1 supply current t a = -40 to +125c, unless otherwise specified table 108. supply current symbol parameter conditions typ max unit i dd supply current in run mode (1) 1. v dd = 5.5 v f cpu =8 mhz (2) 2. cpu running with memory access , all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin ) driven by external sq uare wave, lvd disabled. 69 ma supply current in wait mode f cpu =8 mhz (3) 3. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 2.4 4 supply current in slow mode f cpu = 250 khz (4) 4. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 0.7 1.1 supply current in slow wait mode f cpu = 250 khz (5) 5. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driv en by external square wave, lvd disabled. 0.6 1 i dd supply current in halt mode (6) 6. all i/o pins in output mode with a static value at v ss (no load), lvd disabled. data based on characterization results, tested in production at v dd max and f cpu max. (1) -40c t a +85c <1 10 a -40c t a +125c 50 i dd supply current in awufh mode (7)(8)(9) 7. all i/o pins in input mode with a static value at v dd or v ss (no load). data tested in production at v dd max. and f cpu max. 8. this consumption refers to t he halt period only and not the asso ciated run period which is software dependent. 9. if low consumption is requir ed, awufh mode is recommended. (1) -40c t a +85c 20 50 a -40c t a +125c 300 i dd supply current in active halt mode (1) -40c t a +125c 0.7 1 ma
electrical characteristics st7l34, st7l35, st7l38, st7l39 192/236 doc id 11928 rev 7 figure 78. typical i dd in run mode vs f cpu figure 79. typical i dd in slow mode vs f cpu figure 80. typical i dd in wait mode vs f cpu t b d 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 2.4 2.7 3.3 4 5 6 vdd (v) idd (ma) 8mhz 4mhz 1mhz tbd 0.00 200.00 400.00 600.00 800.00 1000.00 2.4 2.7 3.3 4 5 6 vdd (v) idd (a) 8mhz 4mhz 1mhz 0.0 0.5 1.0 1.5 2.0 2.5 2.4 2.7 3.3 4 5 6 vdd (v) idd (ma) 8mhz 4mhz 1mhz
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 193/236 figure 81. typical i dd in slow-wait mode vs f cpu figure 82. typical i dd vs temperature at v dd = 5 v and f clkin = 16 mhz figure 83. typical i dd vs temperature and v dd at f clkin = 16 mhz 0.00 100.00 200.00 300.00 400.00 500.00 600.00 700.00 800.00 2.4 2.7 3.3 4 5 6 vdd (v) idd (a) 8mhz 4mhz 1mhz tb d 0.00 1.00 2.00 3.00 4.00 5.00 6.00 -45 25 90 110 temperature (c) idd (ma) run wa it slow slow-wait 0.00 1.00 2.00 3.00 4.00 5.00 6.00 -45 25 90 130 temperature (c) idd run (ma) 5 3.3 2.7
electrical characteristics st7l34, st7l35, st7l38, st7l39 194/236 doc id 11928 rev 7 13.4.2 on-chip peripherals table 109. on-chip peripherals symbol parameter conditions typ unit i dd(at) 12-bit autoreload timer supply current (1) 1. data based on a differential i dd measurement between reset confi guration (timer stopped) and a timer running in pwm mode at f cpu =8 mhz. f cpu =4 mhz v dd = 3.0 v 150 a f cpu =8 mhz v dd = 5 v 1000 i dd(spi) spi supply current (2) 2. data based on a differential i dd measurement between reset configuration and a permanent spi master communication (data sent equal to 55h). f cpu =4 mhz v dd = 3.0 v 50 f cpu =8 mhz v dd = 5 v 200 i dd(adc) adc supply current when converting (3) 3. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. f adc =4 mhz v dd = 3.0 v 250 v dd = 5 v 1100 i dd(linsci) linsci supply current when transmitting (4) 4. data based on a differential i dd measurement between linsci runni ng at maximum speed configuration (500 kbaud, continuous transmission of aa +re enabled and linsci off. this measurement includes the pad toggling consumption. f cpu = 8 mhz v dd = 5.0v 650 a
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 195/236 13.5 clock and timing characteristics subject to general operating conditions for v dd , f osc and t a . 13.5.1 general timings table 110. general timings symbol parameter (1) 1. guaranteed by design. not tested in production. conditions min typ (2) 2. data based on typical application software. max unit t c(inst) instruction cycle time f cpu =8 mhz 2312t cpu 250 375 1500 ns t v(it) interrupt reaction time (3) t v(it) = t c(inst) + 10 3. time measured between interrupt event and interrupt vector fetch. dt c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 10 22 t cpu 1.25 2.75 s
electrical characteristics st7l34, st7l35, st7l38, st7l39 196/236 doc id 11928 rev 7 13.5.2 crystal and ceram ic resonator oscillators the st7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. all the information given in this paragraph are based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possibl e to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to t he crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). table 111. oscillator parameters symbol parameter conditions min typ max unit f crosc crystal oscillator frequency (1) 1. when pll is used, please refer to section 7: supply, reset and clock management (f crosc min. is 8 mhz with pll). 216mhz c l1 c l2 recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (r s ) see table 112: typical ceramic resonator characteristics pf table 112. typical ceramic resonator characteristics supplier f crosc (mhz) typical ceramic resonators (1) 1. resonator characteri stics given by the ceramic resonator manufacturer. for more information on these resonators, please consult www.murata.com cl1 [pf] cl2 [pf] supply voltage range (v) reference (2) 2. smd = [-r0: plastic tape package ( ? = 180mm), -b0: bulk] oscillator modes murata 2 cstcc2m00g56-r0 lp or mp (47) (47) 3.0 v to 5.5 v 4 cstcr4m00g55-r0 mp or ms (39) (39) 8 cstce8m00g55-r0 ms or hs (33) (33) 16 cstce16m0v53-r0 hs (15) (15)
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 197/236 13.6 memory characteristics 13.6.1 ram and hardware registers t a = -40 to +125 c, unless otherwise specified. 13.6.2 flash program memory t a = -40 to +85c, unless otherwise specified. table 113. ram and hardware registers symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware register s (only in halt mode). not tested in production. halt mode (or reset) 1.6 v table 114. characteristics of dual voltage hdflash memory symbol parameter cond itions min typ max unit v dd operating voltage for flash write/erase refer to operating range of v dd with t a, section 13.3.1: general operating conditions on page 184 3.0 5.5 v t prog programming time for 1~32 bytes (1) 1. up to 32 bytes can be programmed at a time t a =? 40 to +85 c 5 10 ms programming time for 1.5 kbytes t a = 25 c 0.24 0.48 s t ret (2) 2. data based on reliability test results and monitored in production data retention t a = 55 c (3) 3. the data retention time increases when the t a decreases 20 years n rw write erase cycles t prog = 25 c 1k cycles t prog = 85 c 300 i dd supply current read/write/erase modes f cpu = 8 mhz, v dd = 5.5 v 2.6 (4) 4. guaranteed by design. not tested in production ma no read/no write mode 100 a power down mode/halt 0 0.1
electrical characteristics st7l34, st7l35, st7l38, st7l39 198/236 doc id 11928 rev 7 13.6.3 eeprom data memory t a = -40 to +125c, unless otherwise specified. 13.7 electromagnetic compat ability (emc) characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. 13.7.1 functional electromagn etic susceptibility (ems) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic ev ents until a failure occurs (indicated by the leds). see table 116: electromagnetic test results on page 199 . esd: electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000 - 4 - 2 standard. ftb: a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000 - 4 - 4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. table 115. characteristic s of eeprom data memory symbol parameter conditions min typ max unit v dd operating voltage for eeprom write/erase refer to operating range of v dd with t a, section 13.3.1: general operating conditions on page 184 3.0 5.5 v t prog programming time for 1~32 bytes t a =? 40 to +125 c 5 10 ms t ret (1) 1. data based on reliability test results and monitored in production data retention with 1 k cycling (t prog = ? 40 to +125 c t a = 55 c (2) 2. the data retention time increases when the t a decreases 20 ye a r s data retention with 10 k cycling (t prog = ? 40 to +125 c) 10 data retention with 100 k cycling (t prog = ? 40 to +125 c) 1
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 199/236 designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpectedbehavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). 13.7.2 electromagnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which spec ifies the board an d the loading of each pin. see table 117: emi emissions on page 199 . table 116. electromagnetic test results symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5 v, t a = 25 c, f osc = 8mhz, conforms to iec 1000-4-2 3b v fftb fast transient voltage burst limits to be applied through 100 pf on v dd and v dd pins to induce a functional disturbance v dd = 5 v, t a = 25 c, f osc = 8mhz, conforms to iec 1000-4-4 table 117. emi emissions sym. parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit 8/4 mhz 16/8 mhz s emi peak level (1) 1. data based on characterization results, not tested in production. v dd = 5 v, t a = 25 c, so20 package, conforming to sae j 1752/3 0.1mhz to 30 mhz 15 15 dbv 30 mhz to 130 mhz 13 19 130 mhz to 1 ghz 9 13 sae emi level 2.5 3 -
electrical characteristics st7l34, st7l35, st7l38, st7l39 200/236 doc id 11928 rev 7 13.7.3 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, dlu and lu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: the human body model and the machine model. this test conforms to the jesd22-a114a/a115a standard. static and dynamic latch-up (lu) lu : three complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to application note an1181. dlu : electro-static discharges (one positive then one negative test) are applied to each pin of three samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical valu es, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards. for more details, refer to the application note an1181. electrical sensitivities table 118. esd absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25 c 4000 v v esd(mm) electro-static discharge voltage (machine model) 400 v esd(cdm) electro-static discharge voltage (charged device model) 1000 table 119. latch up results symbol parameter conditions class (1) 1. class description: a class is an st microelectronics inte rnal specification. all it s limits are higher than the jedec specifications, which means when a device belongs to class a it exceeds the jedec standard. class b strictly covers all the jede c criteria (internat ional standard). class b strictly covers all the jedec criteria (international standard) lu static latch-up class t a = 25 c t a = 125 c a dlu dynamic latch-up class v dd = 5.5 v, f osc = 4 mhz, t a = 25 c
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 201/236 13.8 i/o port pin characteristics 13.8.1 general characteristics subject to general operating conditions for v dd , f osc , and t a (-40 to +125c), unless otherwise specified. figure 84. two typical applications with unused i/o pin 1. i/o can be left unconnected if it is configured as output (0 or 1) by the software. this has the advantage of greater emc robustness and lower cost. table 120. i/o general port pin characteristics symbol parameter conditions min typ max unit v il input low level voltage v ss - 0.3 0.3 x v dd v v ih input high level voltage 0.7 x v dd v dd + 0.3 v hys schmitt trigger voltage hysteresis (1) 1. data based on characterization results, not tested in production 400 mv i l input leakage current v ss v in v dd 1 a i s static current consumption induced by each floating input pin (2) 2. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor (see figure 84 ). static peak current value taken at a fixed v in value, based on design simulation and technol ogy characteristics, not tested in production. this value depends on v dd and temperature values floating input mode 400 r pu weak pull-up equivalent resistor (3) 3. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics described in figure 84: two typical applications with unused i/o pin on page 201 ) v in = v ss , v dd = 5 v 50 100 170 k c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time (1) c l = 50 pf between 10% and 90% 25 ns t r(io)out output low to high level rise time (1) t w(it)in external interrupt pulse time (4) 4. to generate an external interrupt, a minimum pulse width must be appli ed on an i/o port pin configured as an external interrupt source. 1t cpu 10k unused i/o port st7 10k unused i/o port st7 v dd
electrical characteristics st7l34, st7l35, st7l38, st7l39 202/236 doc id 11928 rev 7 caution: during normal operation the iccclk pin must be pulled up, internally or externally (external pull-up of 10 k mandatory in noisy environments). this is to avoid entering icc mode unexpectedly during a reset. figure 85. typical i pu vs v dd with v in = v ss 13.8.2 output driving current subject to general operating conditions for v dd , f osc , and t a (-40 to +125 c) unless otherwise specified. to be characterized 0 10 20 30 40 50 60 70 80 90 22.533.5 44.555.56 vdd(v) ipu(ua) ta=140c ta=95c ta=25c ta=-45c table 121. output driving current symbol parameter conditions min typ max unit v ol (1) 1. the i io current sunk must always respect t he absolute maximum rating specified in section 13.2.2: current characteristics on page 182 and the sum of i io (i/o ports and control pins) must not exceed i vss output low level voltage for a standard i/o pin when eight pins are sunk at same time (see figure 88 ) v dd =5 v i io = +5 ma 1.0 v i io = +2 ma 0.4 output low level voltage for a high sink i/o pin when four pins are sunk at same time (see figure 94 ) i io = +20 ma 1.4 i io = +8 ma 0.75 v oh (2) 2. the i io current sourced must always respect the absolute maximum rating specified in section 13.2.2: current characteristics on page 182 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when four pins are sourced at same time (see figure 94 ) i io =-5 ma v dd -1.5 i io =-2 ma v dd -1.0
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 203/236 figure 86. typical v ol at v dd = 3 v figure 87. typical v ol at v dd = 4 v figure 88. typical v ol at v dd = 5 v tbd 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.01123456 lio (m a) vol(v) at vdd = 3v -45c 25c 90c 110c 130c t bd 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.01123456 lio (m a) vol(v) at vdd = 4v -45c 25c 90c 110c 130c tbd 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.01123456 lio (m a) vol(v) at vdd = 5v -45c 25c 90c 110c 130c
electrical characteristics st7l34, st7l35, st7l38, st7l39 204/236 doc id 11928 rev 7 figure 89. typical v ol at v dd = 3 v (high-sink) figure 90. typical v ol at v dd = 4 v (high-sink) figure 91. typical v ol at v dd = 5 v (high-sink) tbd 0.0 0.2 0.4 0.6 0.8 1.0 1.2 581015 lio (m a) vol(v) at vdd = 3v (hs) -45c 25c 90c 110c 130c tbd 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 581015 lio (m a) vol(v) at vdd = 4v (hs) -45c 25c 90c 110c 130c t bd 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 581015 lio (m a) vol (v) at vdd = 5v (hs) -45c 25c 90c 110c 130c
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 205/236 figure 92. typical v dd - v oh at v dd = 3 v figure 93. typical v dd - v oh at v dd = 4 v figure 94. typical v dd - v oh at v dd = 5 v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -0.01-1-2-3-4 lio (m a) vdd - voh at vdd = 3 v -45c 25c 90c 110c 130c tbd 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -0.01-1-2-3-4-5-6 lio (m a) vdd - voh at vdd = 4 v -45c 25c 90c 110c 130c tbd 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -0.01-1-2-3-4-5-6 lio (m a) vdd - voh at vdd = 5 v -45c 25c 90c 110c 130c
electrical characteristics st7l34, st7l35, st7l38, st7l39 206/236 doc id 11928 rev 7 figure 95. typical v ol vs v dd (standard i/os) typical v ol vs v dd (standard i/os) figure 96. typical v dd -v oh vs v dd tb d 0.0 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.5 345 v dd ( v ) vol (v) at llo = 2ma -45c 25c 90c 110c 130c t b d 0.0 0.1 0.1 0.2 0.2 0.3 0.3 0.4 345 vdd (v) vol (v) at llo = 5ma (hs) -45c 25c 90c 110c 130c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 345 vdd (v) vol (v) at llo = 15ma (hs) -45c 25c 90c 110c 130c tbd 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 345 v dd ( v ) vdd - voh (v) at llo = -5ma -45c 25c 90c 110c 130c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 345 v dd ( v ) vdd - voh (v) at llo = -2ma -45c 25c 90c 110c 130c
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 207/236 13.9 control pin characteristics 13.9.1 asynchronous reset pin t a = -40 to +125 c, unless otherwise specified. reset circuit design recommendations the reset network protects the device against parasitic resets. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). whatever the reset source is (internal or external), the user must ensure that the level on the reset pin can go below the v il level specified in section 13.9.1: asynchronous reset pin on page 207 . otherwise the reset is not taken into account internally. because the reset circuit is designed to allow the inte rnal reset to be output in the reset pin, the user must ensure that the curr ent sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in section 13.2.2: current characteristics on page 182 . refer to section 12.2.2: illegal opcode reset on page 177 for details on illegal opcode reset conditions. table 122. asynchronous reset pin symbol parameter conditions min typ max unit v il input low-level voltage v ss - 0.3 0.3 x v dd v v ih input high-level voltage 0.7 x v dd v dd + 0.3 v hys schmitt trigger voltage hysteresis (1) 1 v ol output low-level voltage (1) 1. the i io current sunk must always respect t he absolute maximum rating specified in section 13.2.2: curr ent characteristics on page 182 and the sum of i io (i/o ports and control pins) must not exceed i vss. v dd =5 v i io = +5 ma, t a +85 c t a +125 c 0.5 1.0 (2) 1.2 (2) 2. guaranteed by design. not tested in production. i io = +2 ma, t a +85 c t a +125 c 0.45 0.7 (2) 0.9 (2) r on pull-up equivalent resistor (1)(3) 3. the r on pull-up equivalent resistor is based on a resist ive transistor. specified for voltages on reset pin between v ilmax and v dd. v dd =5 v 10 39 70 k t w(rstl)out generated reset pulse duration internal reset sources 30 s t h(rstl)in external reset pulse hold time (4) 4. to guarantee the reset of the device, a minimum pulse must be applied to the reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. 20 t g(rstl)in filtered glitch duration 200 ns
electrical characteristics st7l34, st7l35, st7l38, st7l39 208/236 doc id 11928 rev 7 reset pin protection when lvd is disabled figure 97. reset pin protection when lvd is disabled reset pin protection when lvd is enabled figure 98. reset pin protection when lvd is enabled note: when the lvd is enabled, it is recommended not to connect a pull-up resistor or capacitor. a 10nf pull-down capacitor is required to filter noise on the reset line. if a capacitive power supply is used, it is recommended to connect a 1 m pull-down resistor to the reset pin to discharge any residual voltage induced by the capacitive effect of the power supply (this adds 5 a to the power consumption of the mcu). tips when using the lvd 1. check that all recommendations related to reset circuit have been applied (see reset circuit design recommendations ) 2. check that the power supply is properly decoupled (100 nf + 10 f close to the mcu). refer to an1709. if this cannot be done, it is recommended to put a 100 nf + 1m pull- down on the reset pin. 3. the capacitors connected on the reset pin and also the power supply are key to avoiding any start-up marginality. in most cases, steps 1 and 2 above are sufficient for a robust solution. othe rwise: replace 10nf pull-down on the reset pin with a 5 f to 20 f capacitor. 0.01f external reset circuit user st7 pulse generator filter r on v dd internal reset watchdog illegal opcode required 0.01f st7 pulse generator filter r on v dd internal reset reset external required 1m optional (note 3) watchdog lvd reset illegal opcode
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 209/236 13.10 communication interface characteristics 13.10.1 serial peripheral interface (spi) subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to section 10: i/o ports for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). table 123. spi characteristics symbol parameter conditions min max unit f sck =1/ t c(sck) spi clock frequency master, f cpu =8mhz f cpu /128 = 0.0625 f cpu /4 = 2 mhz slave, f cpu =8mhz 0 f cpu /2 = 4 t r(sck) spi clock rise and fall time see table 2: device pin description on page 17 t f(sck) t su(ss ) (1) 1. data based on design simulation, not tested in production. ss setup time (2) 2. depends on f cpu . for example, if f cpu = 8 mhz, then t cpu =1/f cpu = 125 ns and t su (ss ) = 550 ns. slave (4 x t cpu ) + 50 ns t h(ss ) (1) ss hold time 120 t w(sckh) (1) sck high and low time master 100 t w(sckl) (1) slave 90 t su(mi) (1) data input setup time master 100 t su(si) (1) slave t h(mi) (1) data input hold time master t h(si) (1) slave t a(so) (1) data output access time slave 0 120 t dis(so) (1) data output disable time 240 t v(so) (1) data output valid time slave (after enable edge) 120 t h(so) (1) data output hold time 0 t v(mo) (1) data output valid time master (after enable edge) 120 t cpu t h(mo) (1) data output hold time 0
electrical characteristics st7l34, st7l35, st7l38, st7l39 210/236 doc id 11928 rev 7 figure 99. spi slave ti ming diagram with cpha = 0 1. measurement points are made at cmos levels: 0.3 x v dd and 0.7 x v dd 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. figure 100. spi slave ti ming diagram with cpha = 1 1. measurement points are made at cmos levels: 0.3 x v dd and 0.7 x v dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha = 0 mosi input miso output cpha = 0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a (so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out see note 2 cpol = 0 cpol = 1 t su(ss ) t h(ss) t dis(so) t h(so) see note 2 bit1 in ss input sck input cpha = 1 mosi input miso output cpha = 1 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out cpol = 0 cpol = 1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 see note 2 t c(sck) hz t v(so) msb in lsb in bit1 in
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 211/236 figure 101. spi master timing diagram 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, the pin status depends of the i/o port configuration. t su(mi) t h(mo) t v(mo) ss input t c(sck) sck input cpha = 0 cpha = 0 cpha=1 cpha = 1 cpol = 0 cpol = 1 cpol=0 cpol = 1 mosi output miso input seenote2 msb out bit6 out lsb out see note 2 msb in bit6 in lsb in t h(mi) t w(sckh) t w(sckl) t r(sck) t f(sck)
electrical characteristics st7l34, st7l35, st7l38, st7l39 212/236 doc id 11928 rev 7 13.11 10-bit adc characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 102. typical application with adc table 124. 10-bit adc characteristics symbol parameter conditions min (1) 1. data based on characterization results, not tested in production typ (2) 2. unless otherwise specifi ed, typical data is based on t a = 25 c and v dd - v ss = 5 v. they are given only as design guidelines and are not tested. max (1) unit f adc adc clock frequency 0.5 4 mhz v ain conversion voltage range (3) 3. when v dda and v ssa pins are not available on the pinout, the adc refers to v dd and v ss v ssa v dda v r ain external input resistor 10 (4) 4. any added external serial resistor downgrades the a dc accuracy (especially fo r resistance greater than 10k ). data based on characterization results, not tested in production. k c adc internal sample and hold capacitor 6 pf t stab stabilization time after adc enable f cpu = 8 mhz, f adc = 4 mhz 0 (5) 5. the stabilization time of the ad converter is masked by the first t load . the first conversion after the enable is then always valid. s t adc conversion time (sample+hold) 3.5 - sample capacitor loading time - hold conversion time 4 10 1/f adc table 125. adc accuracy with 4.5 v < v dd < 5.5 v symbol parameter conditions typ max (1) 1. data based on characterization results, monitored in production to guarantee 99.73 % within max value from -40 c to +125 c ( 3 distribution limits). unit |e t | total unadjusted error f cpu = 8 mhz, f adc = 4 mhz (2)(3) 2.0 3.4 lsb |e o | offset error 0.4 1.7 |e g | gain error 0.4 1.5 |e d | differential linearity error 1.9 3.1 |e l | integral linearity error 1.8 2.9 ainx st7 v dd i l 1a v t 0.6v v t 0.6v c adc v ain r ain 10-bit a/d conversion
st7l34, st7l35, st7l38, st7l39 electrical characteristics doc id 11928 rev 7 213/236 figure 103. adc accura cy characteristics 1. legend: e t = total unadjusted error: maximum deviation between the actual and the ideal transfer curves e o = offset error: deviation between the firs t actual transition and the first ideal one e g = gain error: deviation between the last ideal transition and the last actual one e d = differential linearity error: maximum devi ation between actual steps and the ideal one e l = integral linearity error: maximum deviation between any actual transition and the end point correlation line 2. data based on characterization results over t he whole temperature range, monitored in production. 3. adc accuracy vs negative injection current: inject ing negative current on any of the analog input pins may reduce the accuracy of the conversi on being performed on another analog input. the effect of negative injection current on robust pins is specified in section 13.11: 10-bit adc characteristics on page 212 any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 13.8: i/o port pin characteristics on page 201 does not affect the adc accuracy. table 126. adc accuracy with 3 v < v dd < 3.6 v symbol parameter conditions typ max (1) 1. data based on characterization results, monitored in production to guarantee 99.73 % within max value from -40 c to +125 c ( 3 distribution limits). unit |e t | total unadjusted error f cpu = 4 mhz, f adc = 2 mhz (2)(3) 2. data based on characterization results over t he whole temperature range, monitored in production. 3. adc accuracy vs negative injection current: injecting negative current on any of the analog input pins may reduce the accuracy of the conversi on being performed on another analog input. the effect of negative injection current on robust pins is specified in section 13.11: 10-bit adc characteristics on page 212 any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 13.8: i/o port pin characteristics on page 201 does not affect the adc accuracy. 1.9 3.1 lsb |e o | offset error 0.3 1.2 |e g | gain error 0.3 1 |e d | differential linearity error 1.8 3 |e l | integral linearity error 1.7 2.8 e o e g 1lsb ideal 1lsb ideal v dd v ss ? 1024 ------------------------------- - = v in (lsb ideal ) digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 10211022 1023 1024 (1) (2) e t e d e l (3) v dd v ss (1) = example of an actual transfer curve (2) = ideal transfer curve (3) = end point correlation line
package characteristics st7l34, st7l35, st7l38, st7l39 214/236 doc id 11928 rev 7 14 package characteristics in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at www.st.com. 14.1 package mechanical data figure 104. 20-pin plastic small outline package, 300-mil width table 127. 20-pin plastic small outline package, 300-mil width, mechanical data dim. mm inches min typ max min typ max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.60 13.00 0.496 0.512 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 0 8 0 8 l 0.40 1.27 0.016 0.050 eh a a1 b e d c h x 45 l
st7l34, st7l35, st7l38, st7l39 package characteristics doc id 11928 rev 7 215/236 figure 105. qfn 5x6, 20-terminal very thin fine pitch quad flat no-lead package table 128. qfn 5x6: 20-terminal very thin fine pitch quad flat no-lead package dim. mm inches min typ max min typ min e 0.80 0.0315 l 0.45 0.50 0.55 0.0177 0.0197 0.0217 b (1) 0.25 0.30 0.35 0.0098 0.0118 0.0138 d2 3.30 3.40 3.50 0.1299 0.1339 0.1378 e2 4.30 4.40 4.50 0.1693 0.1732 0.1772 d 5.00 0.1969 e 6.00 0.2362 a 0.80 0.85 0.90 0.0315 0.0335 0.0354 a1 0.00 0.02 0.05 0.0000 0.0008 0.0020 a3 0.02 0.0008 k 0.20 0.0079 n (2) 20 d e 2x 2x 1 2 bottom view top view (ne - 1) x e e (nd - 1) x e nx b k nx l e2 e2/2 d2 d2/2 for odd termin a l s ide for even termin a l s ide det a il a pin 1 id r0.20 a a1 a 3 e e/2 e termin a l tip s ide view l l s e a ting pl a ne s ee det a il a l l c l l c 2 1
package characteristics st7l34, st7l35, st7l38, st7l39 216/236 doc id 11928 rev 7 14.2 packaging for automatic handling the devices can be supplied in trays or with tape and reel conditioning. tape and reel conditioning can be ordered with pin 1 left-oriented or right-oriented when facing the tape sprocket holes as shown in figure 106 . figure 106. pin 1 orientation in tape and reel conditioning see also figure 107: st7fl3x flash commercial product structure on page 222 and figure 108: st7fl3x fastrom commercial product structure on page 223 . 14.3 thermal characteristics nd (3) 4 ne (3) 6 1. dimension b applies to metallized terminals and is measured between 0.15 and 0.30 mm from terminal tip. if the terminal has the optional radius on the other end of the term inal the dimension b should not be measured in that radius area. 2. n is the total number of terminals 3. nd and ne refer to the number of te rminals on each d and e side respectively table 128. qfn 5x6: 20-terminal very thin fine pitch quad flat no-lead package right orientation (eia 481-c compliant) left orientation pin 1 pin 1 table 129. thermal characteristics symbol parameter package value unit r thja package thermal resistance (junction to ambient) so20 70 c/w qfn20 30 t jmax maximum junction temperature (1) 1. the maximum chip-junction temperature is based on technology characteristics so20 150 c qfn20 p dmax maximum power dissipation (2) 2. the maximum power dissipation is obtained from the formula p d = (t j -t a )/r thja . the power dissipation of an application can be defined by th e user with the formula: p d =p int +p port , where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation depe nding on the ports used in the application. so20 < 350 mw qfn20 < 800
st7l34, st7l35, st7l38, st7l39 device configuration and ordering information doc id 11928 rev 7 217/236 15 device configuration and ordering information 15.1 introduction each device is available for production in user programmable versions (flash) as well as in factory coded versions (rom). st7l3x devices are rom versions. st7pl3x devices are factory advanced service technique rom (fastrom) versions: they are factory programmed flash devices. st7fl3 flash devices are shipped to customers with a default program memory content (ffh), while rom/fastrom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be configured by the customer using the option bytes while the rom/fastrom devices are factory-configured. 15.2 option bytes the two option bytes allow the hardware configuration of the microcontroller to be selected. differences in option byte configuration between flash and rom devices are presented in table 130 and are described in section 15.2.1: flash option bytes on page 218 and section 15.2.2: rom option bytes on page 219 . table 130. flash and rom option bytes option byte 0 option byte 1 76543 2 1 0 7 654321 0 name flash aw uck oscrange 2:0 sec 1 sec 0 fm pr fm pw res pll off res osc lvd 1:0 wdg sw wdg halt rom res rop _r rop _d default value 1 1 1 1 1 1 0 0 1 (1) 1. contact your stmi croelectronics support 10 (1) 011 1 1
device configuration and ordering information st7l34, st7l35, st7l38, st7l39 218/236 doc id 11928 rev 7 15.2.1 flash option bytes table 131. option byte 0 description bit bit name function 7 awuck auto wake up clock selection 0: 32 khz oscillator (vlp ) selected as awu clock 1: awu rc oscillator selected as awu clock. note: if this bit is reset, the inte rnal rc oscillator must be selected (option osc = 0). 6:4 oscrange [2:0] oscillator range when the internal rc oscillator is not selected (option osc = 1), these option bits select the range of the resonator oscillator current source or the external clock source. 000: typ. frequency range with resonator (lp) = 1~2 mhz 001: typ. frequency range with resonator (mp) = 2~4 mhz) 010: typ. frequency range with resonator (ms) = 4~8 mhz) 011: typ. frequency range with resonator (hs) = 8~16 mhz) 100: typ. frequency range with resonator (vlp) = 32.768~ khz) 101: external clock on osc1 110: reserved 111: external clock on pb4 note: oscrange[2:0] has no effect when awuck option is set to 0. in this case, the vlp oscillator range is automatically selected as awu clock. 3:2 sec[1:0] sector 0 size definition these option bits indicate the size of sector 0 as follows: 00: sector 0 size = 0.5 kbytes 01: sector 0 size = 1 kbyte 10: sector 0 size = 2 kbytes 11: sector 0 size = 4 kbytes 1fmp_r readout protection readout protection, when select ed provides a protection against program memory content extraction and against write access to flash memory. erasing the option bytes when the fmp_r option is selected will cause the whole memory to be erased first and the device can be reprogrammed. refer to the st7 flash programming reference manual and section 4.5: memory protection on page 25 for more details. 0: readout protection off 1: readout protection on 0fmp_w flash write protection this option indicates if the flash program memory is write protected. warning: when this option is selected, the program memory (and the option bit itself) can never be erased or programmed again. 0: write protection off 1: write protection on note: the option bytes have no address in the memory map and are accessed only in programming mode (for example using a standard st7 programming tool). the default content of the flash is fixed to ffh.
st7l34, st7l35, st7l38, st7l39 device configuration and ordering information doc id 11928 rev 7 219/236 15.2.2 rom option bytes table 132. option byte 1 description bit bit name function 7 - reserved, must be set to 1 (1) 1. contact your stmicroelectronic support 6 plloff pll disable this option bit enables or disables the pll. 0: pll enabled 1: pll disabled (bypassed) 5 - reserved, must be set to 0 (1) 4osc rc oscillator selection this option bit enables selection of the internal rc oscillator. 0: rc oscillator on 1: rc oscillator off note: to improve clock stability and frequency accuracy when the rc oscillator is selected, it is recommended to place a decoupling capacitor, typically 100 nf, between the v dd and v ss pins as close as possible to the st7 device. 3:2 lvd[1:0] low voltage selection these option bits enable the voltage det ection block (lvd and avd) with a selected threshold to the lvd and avd: 11: lvd off 10: lvd on (highest voltage threshold) 1wdgsw hardware or software watchdog 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) 0wdghalt watchdog reset on halt 0: no reset generation when entering halt mode 1: reset generation when entering halt mode table 133. option byte 0 description bit bit name function 7 awuck auto wake up clock selection 0: 32 khz oscillator (vlp ) selected as awu clock 1: awu rc oscillator selected as awu clock. note: if this bit is reset, the inte rnal rc oscillator must be selected (option osc = 0).
device configuration and ordering information st7l34, st7l35, st7l38, st7l39 220/236 doc id 11928 rev 7 6:4 oscrange[2:0] oscillator range when the internal rc oscillator is not selected (option osc = 1), these option bits select the range of the resonator oscillator current source or the external clock source. 000: typ. frequency range with resonator (lp) = 1~2 mhz 001: typ. frequency range with resonator (mp) = 2~4 mhz) 010: typ. frequency range with resonator (ms) = 4~8 mhz) 011: typ. frequency range with resonator (hs) = 8~16 mhz) 100: typ. frequency range with resonator (vlp) = 32.768~ khz) 101: external clock on osc1 110: reserved 111: external clock on pb4 note: oscrange[2:0] has no effect when awuck option is set to 0. in this case, the vlp oscillator range is automatically selected as awu clock 3:2 - reserved, must be set to 1 1rop_r readout protection for rom this option is for read protection of rom 0: readout protection off 1: readout protection on 0rop_d readout protection for data eeprom this option is for read protection of eeprom memory. 0: readout protection off 1: readout protection on table 134. option byte 1 description bit bit name function 7 - reserved, must be set to 1 (1) 6plloff pll disable this option bit enables or disables the pll. 0: pll enabled 1: pll disabled (bypassed) 5 - reserved, must be set to 0 (1) 4osc rc oscillator selection this option bit enables selection of the internal rc oscillator. 0: rc oscillator on 1: rc oscillator off note: to improve clock stability and frequency accuracy when the rc oscillator is selected, it is recommended to place a decoupling capacitor, typically 100 nf, between the v dd and v ss pins as close as possible to the st7 device. 3:2 lvd[1:0] low voltage selection these option bits enable the voltage detection block (lvd and avd) with a selected threshold to the lvd and avd: 11: lvd off 10: lvd on (highest voltage threshold) table 133. option byte 0 description bit bit name function
st7l34, st7l35, st7l38, st7l39 device configuration and ordering information doc id 11928 rev 7 221/236 15.3 device ordering informati on and transfer of customer code customer code is made up of the rom/fastrom contents and the list of the selected options (if any). the rom/fastrom contents are to be sent on a diskette or by electronic means, with the s19 hexadecimal file generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmicroelectronics using the correctly completed option list appended on page 225 . refer to application note an1635 for information on the counter listing returned by st after code has been transferred. the stmicroelectronics sales organization will be pleased to provide detailed information on contractual points. 1wdgsw hardware or software watchdog 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) 0 wdghalt watchdog reset on halt 0: no reset generation when entering halt mode 1: reset generation when entering halt mode 1. contact your stmicroelectronics support table 134. option byte 1 description bit bit name function
device configuration and ordering information st7l34, st7l35, st7l38, st7l39 222/236 doc id 11928 rev 7 figure 107. st7fl3x flash commercial product structure 1. for a list of available options (e.g. memory size, package) and or derable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you. st7 f l34 f 2 m a x s product class st7 microcontroller pin count f = 20 pins package type m = so u = qfn example: sub-family type l34 = without data eeprom, without lin l35 = without data eeprom, with lin l38 = with data eeprom, without lin l39 = with data eeprom, with lin family type f = flash temperature range a = -40 c to 85 c c = -40 c to 125 c program memory size 2 = 8 kbytes tape and reel conditioning options (left blank if tray) tr or r = pin 1 left-oriented tx or x = pin 1 right-oriented (eia 481-c compliant) ecopack/fab code blank or e = lead-free ecopack ? phoenix fab s = lead-free ecopack ? catania fab
st7l34, st7l35, st7l38, st7l39 device configuration and ordering information doc id 11928 rev 7 223/236 figure 108. st7fl3x fastrom commercial product structure st7 p l34 m a /xxx x s product class st7 microcontroller package type m = so u = qfn example: sub-family type l34 = without data eeprom, without lin l35 = without data eeprom, with lin l38 = with data eeprom, without lin l39 = with data eeprom, with lin family type p = fastrom temperature range a = -40 c to 85 c c = -40 c to 125 c tape and reel conditioning options (left blank if tray) tr or r = pin 1 left-oriented tx or x = pin 1 right-oriented (eia 481-c compliant) ecopack/fab code blank or e = lead-free ecopack ? phoenix fab s = lead-free ecopack ? catania fab code name defined by stmicroelectronics. denotes rom code, pinout and program memory size.
device configuration and ordering information st7l34, st7l35, st7l38, st7l39 224/236 doc id 11928 rev 7 figure 109. rom commercial product code structure st7 l34 m a /xxx x s product class st7 microcontroller package type m = so u = qfn example: sub-family type l34 = without data eeprom, without lin l35 = without data eeprom, with lin l38 = with data eeprom, without lin l39 = with data eeprom, with lin temperature range a = -40 c to 85 c c = -40 c to 125 c tape and reel conditioning options (left blank if tray) tr or r = pin 1 left-oriented tx or x = pin 1 right-oriented (eia 481-c compliant) ecopack/fab code blank or e = lead-free ecopack ? phoenix fab s = lead-free ecopack ? catania fab code name defined by stmicroelectronics. denotes rom code, pinout and program memory size.
st7l34, st7l35, st7l38, st7l39 device configuration and ordering information doc id 11928 rev 7 225/236 1. not all configurations are available. see section 15.2: option bytes on page 217 for authorized option byte combinations. st7l3 fastrom and rom microcontroller option list (last update: october 2007) customer: ..................................................................... address: ..................................................................... ..................................................................... contact: ..................................................................... phone no: ..................................................................... reference/fastrom or rom code: ............................... the fastrom/rom code name is assigned by stmicroelectronics. fastrom/rom code must be sent in .s19 fo rmat. .hex extension cannot be processed. device type/memory size/package (check only one option): --------------------------------------------------------------------------------------------- fastrom device 8k | so20 | qfn20 --------------------------------------------------------------------------------------------- | [ ] st7pl34f2m | [ ] st7pl34f2u | [ ] st7pl35f2m | [ ] st7pl35f2u | [ ] st7pl38f2m | [ ] st7pl38f2u | [ ] st7pl39f2m | [ ] st7pl39f2u ----------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------- rom device 8k | so20 | qfn20 ---------------------------------------------------------------------------------------------- | [ ] st7l34f2m | [ ] st7l34f2u | [ ] st7l35f2m | [ ] st7l35f2u | [ ] st7l38f2m | [ ] st7l38f2u | [ ] st7l39f2m | [ ] st7l39f2u ----------------------------------------------------------------------------------------------- conditioning: [ ] tape and reel [ ] tube (check only one option) special marking: [ ] no [ ] yes ".........................." authorized characters are letters, digits, '.', '-', '/' and spaces only. maximum character count: so20 (8 char. max): .......................... qfn20 (8 char. max): .......................... temperature range: [ ] a (-40 to +85 c) [ ] c (-40 to +125 c) awuck selection: [ ] 32 khz oscillator [ ] awu rc oscillator clock source selection: [ ] resonator [ ] vlp: very low power resonator (32 to 100 khz) [ ] lp: low power resonator (1 to 2 mhz) [ ] mp: medium power resonator (2 to 4 mhz) [ ] ms: medium speed resonator (4 to 8 mhz) [ ] hs: high speed resonator (8 to 16 mhz) [ ] external clock [ ] on pb4 [ ] on osci [ ] internal rc oscillator pll: [ ] disabled [ ] enabled lvd reset threshold: [ ] disabled [ ] enabled (highest voltage threshold) watchdog selection: [ ] software activation [ ] hardware activation watchdog reset on halt: [ ] disabled [ ] enabled flash devices only: sector 0 size: [ ] 0.5 k [ ] 1 k [ ] 2 k [ ] 4 k readout protection: [ ] disabled [ ] enabled flash write protection: [ ] disabled [ ] enabled rom devices only rom readout protection: [ ] disabled [ ] enabled eedata readout protection:[ ] disabled [ ] enabled comments: ............................. supply operating range in the application: ............................. notes: ............................. date: ............................. signature: ...........................
device configuration and ordering information st7l34, st7l35, st7l38, st7l39 226/236 doc id 11928 rev 7 15.4 development tools 15.4.1 starter kits st offers complete, affordable starter kits . starter kits are complete, affordable hardware/software tool packages that include features and samples to help you quickly start developing your application. 15.4.2 development and debugging tools application development for st7 is supported by fully optimizing c compilers and the st7 assembler-linker toolchain, which are all seam lessly integrated in the st7 integrated development environments in order to facilit ate the debugging and fine-tuning of your application. the cosmic c compile r is available in a free version that outputs up to 16 kbytes of code. the range of hardware tools includes full featured st7-emu3 series emulators, cost effective st7-dvp3 series emulators and the low-cost rlink in-circuit debugger/programmer. these tools are supported by the st7 toolset from stmicroelectronics, which includes the stvd7 integrated development environment (ide) with high-level language debugger, editor, project manager and integrated programming interface. 15.4.3 programming tools during the development cycle, the st7-dvp3 and st7-emu3 series emulators and the rlink provide in-circuit prog ramming capability for programmi ng the flash microcontroller on your application board. st also provides a low-cost dedicated in-circuit programmer, the st7-stick, as well as st7 socket boards which provide all the sockets required for programming any of the devices in a specific st7 subfamily on a platform that can be used with any tool with in- circuit programming capability for st7. for production programming of st7 devices, st?s third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment.
st7l34, st7l35, st7l38, st7l39 device configuration and ordering information doc id 11928 rev 7 227/236 15.4.4 order codes for developm ent and programming tools table 135 below lists the ordering codes for the st7l3x development and programming tools. for additional ordering codes for spare parts and accessories, refer to the online product selector at www.st.com/mcu. table 135. st7l3 development and programming tools supported products in-circuit debugger, rlink series (1) 1. available from st or from raisonance emulator programming tool starter kit with demo board starter kit without demo board dvp series emu series in-circuit programmer st socket boards and epbs st7fl34 st7flite- sk/rais (2)(3) 2. usb connection to pc 3. parallel port connection to pc stx- rlink (2)(3) st7mdt10- dvp3 (4) 4. add suffix /eu, /uk or /us for the power supply for your region st7mdt10 -emu3 st7-stick stx-rlink (4)(5) 5. includes connection kit for dip16/so16 only. see ?how to order an emu or dvp? in st product and tool selection guide for connecti on kit ordering information st7sb10- 123 (4) st7fl35 st7fl38 st7fl39
important notes st7l34, st7l35, st7l38, st7l39 228/236 doc id 11928 rev 7 16 important notes 16.1 clearing active interru pts outside interrupt routine when an active interrupt request occurs at the same time as the related flag or interrupt mask is being cleared, the cc register may be corrupted. concurrent interrupt context the symptom does not occur when the interrupts are handled normally, that is, when: the interrupt request is cleared (flag reset or interrupt mask) within its own interrupt routine the interrupt request is cleared (flag reset or interrupt mask) within any interrupt routine the interrupt request is cleared (flag reset or interrupt mask) in any part of the code while this interrupt is disabled if these conditions are not met, the symptom is avoided by implementing the following sequence: perform sim and rim operation before and after resetting an active interrupt request. example: sim reset flag or interrupt mask rim 16.2 linsci limitations 16.2.1 header time-out does not prevent wake-up from mute mode normally, when linsci is configured in lin slave mode, if a header time-out occurs during a lin header reception (that is, header length > 57 bits), the lin header error bit (lhe) is set, an interrupt occurs to inform the application but the linsci should stay in mute mode, waiting for the next header reception. problem description the linsci sampling period is tbit/16. if a lin header time-out occurs between the 9th and the 15th sample of the identifier field stop bit (refer to figure 110 ), the linsci wakes up from mute mode. nevertheless, lhe is set and lin header detection flag (lhdf) is kept cleared. in addition, if lhe is reset by software before this 15th sample (by accessing the scisr register and reading the scidr register in the li nsci interrupt routine), the linsci will generate another linsci interrupt (due to the rdrf flag setting).
st7l34, st7l35, st7l38, st7l39 important notes doc id 11928 rev 7 229/236 figure 110. header reception event sequence impact on application software may execute the interrupt routine twice after header reception. moreover, in reception mode, as the receiver is no longer in mute mode, an interrupt is generated on each data byte reception. workaround the problem can be detected in the linsci interrupt routine. in case of time-out error (lhe is set and lhlr is loaded with 00h), the software can check the rwu bit in the scicr2 register. if rwu is cleared, it can be set by software (refer to figure 111 ). the workaround is shown in bold characters. figure 111. linsci interrupt routine lin synch lin synch identifier field field break t header active mode is set rdrf flag is set critical window id field stop bit (rwu is cleared) @interrupt void linsci_it ( void ) /* linsci interrupt routine */ { /* clear flags */ scisr_buffer = scisr; scidr_buffer = scidr; if ( scisr_buffer & lhe )/* header error ? */ { if (!lhlr)/* header time-out? */ { if ( !(scicr2 & rwu) )/* active mode ? */ { _asm("sim");/* disable interrupts */ scisr; scidr;/* clear rdrf flag */ scicr2 |= rwu;/* set mute mode */ scisr; scidr;/* clear rdrf flag */ scicr2 |= rwu;/* set mute mode */ _asm("rim");/* enable interrupts */ } } } } example using cosmic compiler syntax
revision history st7l34, st7l35, st7l38, st7l39 230/236 doc id 11928 rev 7 17 revision history table 136. revision history date revision changes jun-2004 1 first release 23-dec-2005 2 changed temperature range (added -40 to +125c) removed references to 1% internal rc accuracy; changed figure 4: memory map on page 19 removed reference to amplifier for adcdrl in ta bl e 3 : h a r d w a r e register map on page 20 and in section 11.6.6: register description on page 168 and replaced ? data register low? by ?control and data register low?; changed section 4.4: icc interface on page 23 and added note 6 modified note on clock stability and on icc mode in section 7.1: internal rc oscillator adjustment on page 38 added text in note 1 in table 7: rccr calibration registers on page 38 added rccr1 ( figure 4 on page 19 and section 7: supply, reset and clock management on page 38 ) added note to section 7.5: reset sequence manager (rsm) on page 43 ; added note 3 after table 24: i/o port mode options on page 71 exit from halt mode during an overflow event set to ?no? in section 11.2.4: low power modes on page 89 removed watchdog section in section 11.3: lite timer 2 (lt2) on page 102 table 48: effect of low power modes on lite timer 2 on page 105 and table 49: lite timer 2 interrupt c ontrol/wake-up capability on page 105 expanded added important note in master mode operation on page 112 changed procedure description in transmitter on page 127 in extended baud rate generation on page 131 : corrected equation for rx to read: rx = f cpu /(16 x erpr x pr x rr), {instead of rx = f cpu /(16 x erpr x pr x tr)} added note on illegal opcode reset to section 12.2.2: illegal opcode reset on page 177 ; changed section 13.1.2: typical values on page 180 changed electrical characteristics in the following sections: section 13.3: operating conditions on page 184 , section 13.4: supply current characteristics on page 191 , section 13.6: memory characteristics on page 197 , section 13.7.3: absolute maximum ratings (electrical sensitivity) on page 200 , section 13.8: i/o port pin characteristics on page 201 , section 13.9: control pin characteristics on page 207 , section 13.10: communication interface characteristics on page 209 and section 13.11: 10-bit ad c characteristics on page 212 modified section 14: package characteristics on page 214 changed section 15.2: option bytes on page 217 (opt 5 of option byte 1), section 15.3: device ordering information and transfer of customer code on page 221 and section 15.4: development tools on page 226 changed option list, added section 16: important notes on page 228
st7l34, st7l35, st7l38, st7l39 revision history doc id 11928 rev 7 231/236 06-mar-2006 3 removed all x4 pll option references from document changed read operation section in section 5.3: memory access on page 28 changed note figure 8: data eeprom wr ite operation on page 29 . changed section 5.5: access error handling on page 30 replaced 3.3 v with 3.6 v in section 7.2: phase locked loop on page 39 changed master mode operation on page 112 : added important note changed section 13.1.2: typical values on page 180 changed section 13.3.1: general operating conditions on page 184 and added note on clock stability and frequency accuracy; removed the following figure: pll f cpu /f cpu vs time changed section 13.3.2: operating conditions with low voltage detector (lvd) on page 188 and section 13.3.4: internal rc oscillator and pll on page 190 changed section 13.4.1: supply current on page 191 and added notes changed table 115: characteristics of eeprom data memory on page 198 removed note 6 from section 13.6: memory characteristics on page 197 changed section 13.6.2: flash program memory on page 197 ; changed section 13.6.3: eeprom data memory on page 198 changed values in section 13.7.2: electromagnetic interference (emi) on page 199 changed absolute maximum ratings in table 118: esd absolute maximum ratings on page 200 changed section 13.8.1: general characteristics on page 201 and section 13.8.2: output driving current on page 202 changed section 13.9.1: asynchronous reset pin on page 207 (changed values, removed references to 3 v and added note 5) changed section 13.11: 10-bit adc characteristics on page 212 : changed values in adc accuracy tables and added note 3 changed notes in section 14.3: thermal characteristics on page 216 changed section 15: device configuration and ordering information on page 217 changed table 130: soldering compatibility (wave and reflow soldering process) on page 208 added note to osc option bit in section 15.2: option bytes on page 217 changed configuration of bit 7, option byte 1, in table 130: flash and rom option bytes on page 217 changed device type/memory size/package and pll options in st7l1 fastrom and rom microcontroller option list on page 257. table 136. revision history (continued) date revision changes
revision history st7l34, st7l35, st7l38, st7l39 232/236 doc id 11928 rev 7 17-mar-2006 4 changed caution text in section 8.2: external interrupts on page 52 changed external interrupt function in section 10.2.1: input modes on page 69 changed table 101 and ta b l e 1 0 2 changed table 103 and ta b l e 1 0 4 changed figure 98: reset pin protection when lvd is enabled on page 208 removed emc protective circuitry in figure 97: reset pin protection when lvd is disabled on page 208 (device works correctly without these components) removed section ?linsci wrong break duration? from section 16: important notes on page 228 20-dec-2006 5 replaced ?st7l3? with ?st7l34, st7l35, st7l38, st7l39? in document name and added qfn20 package to package outline on cover page. changed section 1: description on page 14 transferred device summary table from cover page to section 1: description on page 14 added qfn20 package to the device summary table in section 1: description on page 14 figure 1: general block diagram on page 15 : replaced autoreload timer 2 with autoreload timer 3 added figure 3: 20-pin qfn package pinout on page 16 to section 2 table 2: device pin description on page 17 : - added qfn20 package pin numbers - removed caution about pb0 and pb1 negative current injection restriction figure 4: memory map on page 19 : removed references to note 2 table 3: hardware register map on page 20 : - changed register name for ltcntr - changed reset status of registers ltcsr1, atcsr and sicsr - changed note 3 changed last paragraph of section 5.5: access error handling on page 30 added caution about avoiding unwanted behavior during reset sequence in section 7.5.1: introduction on page 43 figure 17: reset sequences on page 46 : replaced ?t cpu ? with ?t cpu ? at bottom of figure changed notes in section 7.6.1: low voltage detector (lvd) on page 46 figure 19: reset and supply management block diagram on page 48 : removed names from sicsr bits 7:5 changed reset value of bits cr0 and cr1 from 0 to 1 in section 7.6.4: register description on page 49 table 16: interrupt sensitivity bits on page 55 : restored table number (inadvertantly removed in rev. 3) figure 34: watchdog block diagram on page 76 : changed register label changed register name and label in section 11.1.6: register description on page 78 added note for rom devices only to pwm mode on page 80 table 136. revision history (continued) date revision changes
st7l34, st7l35, st7l38, st7l39 revision history doc id 11928 rev 7 233/236 20-dec-2006 5 cont?d replaced bit name ovie1 with ovfie1 in table 35: at3 interrupt control/wake-up capability on page 90 changed description of bits 11:0 in counter register 1 high (cntr1h) on page 91 , counter register 1 low (cntr1l) on page 91 and table 37: cntr1h and cntr1l regi ster descriptions on page 92 changed name of register atr1h and atr1l in autoreload register high (atr1h) , autoreload register low (atr1l) and table 38: atr1h and atr1l register descriptions on page 93 changed name of register atcsr2 in timer control register2 (atcsr2) and table 44: atcsr2 register description on page 98 changed name of register atr2h and atr2l in autoreload register2 high (atr2h) , autoreload register2 low (atr2l) and table 45: atr2h and atr2l register descriptions on page 99 changed name of register ltcsr1 in lite timer control/status register (ltcsr1) and table 53: ltcsr1 register description on page 107 . changed names of register s spidr, spicr and spicsr in section 11.4.8: register description on page 119 figure 64: lin synch field measurement on page 150 : - replaced ?t cpu ? with ?t cpu ? - replaced ?t br ? with ?t br ? modified table 98: current characteristics on page 182 : - changed i io values - removed ?injected current on pb0 and pb1 pins? from table - removed note 5 ?no negative current injection allowed on pb0 and pb1 pins? restored symbol for pll jitter in table 102: operating conditions (tested for ta = -40 to +125 c) @ vdd = 4.5 to 5.5 v on page 185 (inadvertantly changed in rev. 4) added note 5 to table 105: operating conditions with low voltage detector on page 188 specified applicable t a in table 113: ram and hardware registers on page 197 , table 114: characteristics of dual voltage hdflash memory on page 197 and table 115: characteristics of eeprom data memory on page 198 changed t a for programming time for 1~32 bytes and changed t prog from 125c to 85c for write erase cycles in table 114: characteristics of dual voltage hdflash memory on page 197 figure 84: two typical applications with unused i/o pin on page 201 : replaced st7xxx with st7 table 121: output driving current on page 202 : added table number and title table 122: asynchronous reset pin on page 207 : added table number and title replaced st72xxx with st7 in figure 98: reset pin protection when lvd is enabled on page 208 and figure 97: reset pin protection when lvd is disabled on page 208 changed section 13.10.1: serial peripheral interface (spi) on page 209 figure 100: spi slave timing diagram with cpha = 1 on page 210 : replaced cpha = 0 with cpha = 1 figure 101: spi master timing diagram on page 211 : repositioned t v(mo) and t h(mo) table 136. revision history (continued) date revision changes
revision history st7l34, st7l35, st7l38, st7l39 234/236 doc id 11928 rev 7 20-dec-2006 5 cont?d table 124: 10-bit adc characteristics on page 212 : added table number and title changed p dmax value for so20 package in table 129: thermal characteristics on page 216 removed text concerning lqfp, tqfp and sdip packages from section 15: device configuration and ordering information on page 217 . figure 102: typical application with adc on page 212 : replaced st72xxx with st7 changed typical and maximum values and added table number and title to table 125: adc accuracy with 4.5 v < vdd < 5.5 v on page 212 and to table 126: adc accuracy with 3 v < vdd < 3.6 v on page 213 added figure 105: qfn 5x6, 20-terminal very thin fine pitch quad flat no-lead package on page 215 added qfn20 package to table 129: thermal characteristics on page 216 table 130: soldering compatibility (wave and reflow soldering process) on page 208 : - changed title of ?plating material? column - added qfn package - removed note concerning pb-package temperature for leadfree soldering compatibility changed section 15.2: option bytes on page 217 to add different configurations between flash and rom devices for option byte 0 removed ?automotive? from title of section 15.3: device ordering information and transfer of customer code on page 221 removed ?supported part numbers? table from section 15.3: device ordering information and transfer of customer code on page 221 added figure 107: st7fl3x flash commercial product structure on page 222 added table 135: flash user programmable device types on page 213 added figure 108: st7fl3x fastrom co mmercial product structure on page 223 added table 136: fastrom factory coded device types on page 215 added figure 109: rom commercial product code structure on page 224 added table 137: rom factory coded device types on page 216 updated st7l3 fastrom and rom microcontroller option list on page 225 changed section 15.4: development tools on page 226 and table 135: st7l3 development and programming tools on page 227 updated disclaimer (last page) to include a mention about the use of stproducts in automotive applications 02-aug-2010 6 changed the description of internal rc oscillator from ?high precision? to ?1% in clock, reset and supply management on cover page and in section 7.4.3: internal rc oscillator on page 42 table 7: rccr calibration registers on page 38 : added footnote 2 section 7.6.1: low voltage detector (lvd) on page 46 : changed the sentence about the lvd to read that it can be enabled with ?highest voltage threshold? instead of ?low, medium or high? figure 26: halt mode flowchart on page 61 : added footnote 5 table 136. revision history (continued) date revision changes
st7l34, st7l35, st7l38, st7l39 revision history doc id 11928 rev 7 235/236 02-aug-2010 6 cont?d figure 31: awufh mode flowchart on page 66 : added footnote 5 table 101: operating conditions (tested for ta = -40 to +125 c) @ vdd = 4.5 to 5.5 v on page 185 : changed f rc and acc rc flash values table 102: operating conditions (tested for ta = -40 to +125 c) @ vdd = 4.5 to 5.5 v on page 185 : changed acc pll ?typical? value table 103: operating conditions (tested for ta = -40 to +125 c) @ vdd = 3.0 to 3.6 v on page 186 : changed f rc and acc rc flash values table 118: esd absolute maximum ratings on page 200 : changed values of v esd(hbm) and v esd(hbm) . table 132: option byte 1 description on page 219 : added ?must be set to 1? to option bit 7 and ?must be set to 0? to option bit 5 table 133: option byte 0 description on page 219 : added ?must be set to 1? to option bits 3:2 updated figure 107: st7fl3x flash commercial product structure , figure 108: st7fl3x fastrom commercial product structure and figure 109: rom commercial product code structure 11-oct-2010 7 updated fclkin test conditions and maximum values in table 100: general operating conditions and figure 72: fclkin maximum operating frequency vs vdd supply voltage table 136. revision history (continued) date revision changes
st7l34, st7l35, st7l38, st7l39 236/236 doc id 11928 rev 7 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com


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